Rajeev Kumar Dokania

Method of integrating a memory device with a transistor by hybrid bonding

Amplitude modulation for writing to a multi-level bit-cell

Apparatus to reduce polarization targets or improve memory density for non-linear polar material based memory

Fabricating non-linear polar material based capacitors for memory and logic

Method of fabricating transistors and stacked non-planar capacitors for memory and logic applications

Memory device fabrication through wafer bonding

Asynchronous full-adder with majority or minority gates to generate an enable or an acknowledgement

Asynchronous full-adder with majority or minority gates to generate sum true output

Ferroelectric or paraelectric based low power multiplier

Sequential reset mechanism for a chain of majority or minority gates having non-linear polar material

Ripple carry adder with ferroelectric or paraelectric wide-input minority or majority gates

Diode connected non-linear input capacitors based majority gate

Method of integrating a capacitor including a non-linear polar material with a transistor through wafer bonding

Gate coupled non-linear polar material based capacitors for memory and logic

Non-linear polar material based low power multiplier with transmission-gate based reset mechanism

Time decoupled write operations for non-linear polar material based memory

Asynchronous full-adder with majority or minority gates to generate carry-out true output

Asynchronous full-adder with majority or minority gates to generate carry-out false output

Asynchronous full-adder with majority or minority gates to generate sum false output

Methods of fabricating planar capacitors on a shared plate electrode

Ferroelectric or paraelectric wide-input minority or majority gate based low power adder

Capacitor devices with shared electrode and methods of fabrication

HIGH BANDWIDTH THREE-DIMENSIONAL SYSTEM-ON-CHIP

Apparatus and method to improve sensing noise margin in a non-linear polar material based bit-cell

THREE-DIMENSIONAL STACK OF HETEROGENEOUS MEMORY AND COMPUTE DIES

Methods of fabricating trench capacitors on a shared plate electrode

Stacked non-planar capacitors based multi-function linear threshold gate with input based adaptive threshold

Multi-cycle reset mechanism for a chain of majority gates having non-linear polar material

Integration of 2T-C for memory and logic applications

Stacked capacitors with shared electrodes and methods of fabrication

Planar capacitors with shared electrode and methods of fabrication

Multi-function threshold gate with input based adaptive threshold and with stacked non-planar paraelectric capacitors

Multi-function linear threshold gate with input based adaptive threshold

PILLAR CAPACITOR STRUCTURE FOR HIGH DENSITY MEMORY APPLICATIONS

Exclusive-or logic gate with non-linear input capacitors

Multiplier with non-linear polar material

Random swap injection

Method of adjusting threshold of a linear capacitive-input circuit

Memory array with buried or backside word-line

Area optimized ferroelectric or paraelectric based low power multiplier

Method of fabricating transistors and stacked planar capacitors for memory and logic applications

Ferroelectric or paraelectric based low power multiplier array

Majority or minority based low power checkerboard carry save multiplier with inverted multiplier cells

Ultra high-bandwidth artificial intelligence (AI) processor with DRAM under the processor

Capacitor integrated with a transistor for logic and memory applications

Multi-die mapping matrix multiplication

Trench capacitors with shared electrode

3D stack of split graphics processing logic dies

Embedded memory adjacent to non-memory

Stacked planar capacitors based multi-function linear threshold gate with input based adaptive threshold

PLANAR FERROELECTRIC MEMORY DEVICE

Non-linear polar material based flip-flop

NON-LINEAR POLAR MATERIAL BASED MULTI-CAPACITOR BIT-CELL WITH SHARED GAIN ELEMENT AND ACCESS TRANSISTOR

NON-LINEAR POLAR MATERIAL BASED MULTI-CAPACITOR BIT-CELL WITH MULTI-WAY SHARING OF GAIN ELEMENT WITH SERIES TRANSISTOR

Read disturb mitigation for non-linear polar material based multi-capacitor bit-cell

Multi-input threshold gate having stacked and folded non-planar capacitors

Method of forming an artificial intelligence processor with three-dimensional stacked memory

METHOD OF FORMING FERROELECTRIC CHIPLET IN A MULTI-DIMENSIONAL PACKAGING WITH I/O SWITCH EMBEDDED IN A SUBSTRATE OR INTERPOSER

Reset mechanism for an adder or a multiplier having paraelectric material

Area oriented logic synthesis

METHOD OF FORMING A MAJORITY GATE BASED LOW POWER FERROELECTRIC BASED ADDER WITH RESET MECHANISM

FERROELECTRIC CAPACITOR INTEGRATED WITH A LOGIC DEVICE

NON-LINEAR POLAR MATERIAL BASED MULTI-CAPACITOR BIT-CELL WITH SHARED GAIN ELEMENT WITH SERIES TRANSISTOR

NON-LINEAR POLAR MATERIAL BASED MULTI-CAPACITOR BIT-CELL WITH SHARED GAIN ELEMENT WITH SERIES TRANSISTOR AND INDIVIDUAL ACCESS TRANSISTOR

METHOD OF MEMORY DEVICE FABRICATION THROUGH ITERATIVE MULTILAYER STACK DEVELOPMENT

Ripple carry adder with inverted ferroelectric or paraelectric based adders

Low power multiplier with non-linear polar material based reset mechanism with sequential reset

Method for conditioning majority or minority gate

Memory bit-cell with stacked and folded planar capacitors

FERROELECTRIC MEMORY CHIPLET IN A MULTI-DIMENSIONAL PACKAGING WITH I/O SWITCH EMBEDDED IN A SUBSTRATE OR INTERPOSER

Write disturb mitigation for column multiplexed non-linear polar material based multi-capacitor bit-cell

Multi-input threshold gate having stacked and folded planar capacitors with and without offset

Ferroelectric memory chiplet in a multi-dimensional packaging

METHOD OF FORMING CAPACITORS THROUGH WAFER BONDING

METHOD OF FABRICATING MEMORY DEVICES INCLUDING B-SITE DOPANTS AND LOGIC DEVICES THROUGH WAFER BONDING

METHOD OF FORMING STACKED CAPACITORS THROUGH WAFER BONDING

NON-LINEAR POLAR MATERIAL BASED MULTI-CAPACITOR HIGH DENSITY BIT-CELL

1TnC memory bit-cell having stacked and folded non-planar capacitors

Trench capacitors with continuous dielectric layer and methods of fabrication

Planar and trench capacitors with hydrogen barrier dielectric for logic and memory applications and methods of fabrication

Method and apparatus for heuristic-based power gating of non-CMOS logic and CMOS based logic

Iterative monetization of precursor in process development of non-linear polar material and devices

Planar and trench capacitors for logic and memory applications and methods of fabrication

Method and apparatus for managing power in a multi-dimensional packaging

Asynchronous consensus circuit with stacked ferroelectric non-planar capacitors

Planar and trench capacitors for logic and memory applications

Asynchronous consensus circuit with majority gate based on non-linear capacitors

Multi-level hydrogen barrier layers for memory applications and methods of fabrication

Method and apparatus for managing power of ferroelectric or paraelectric logic and CMOS based logic

1TnC memory bit-cell having stacked and folded planar capacitors with lateral offset

Pocket flow for trench capacitors integrated with planar capacitors on a same substrate and method of fabrication

Planar and trench capacitors with hydrogen barrier dielectric for logic and memory applications

Multi-function threshold gate with input based adaptive threshold and with stacked non-planar ferroelectric capacitors

Planar capacitors with non-linear polar material staggered on a shared electrode

Majority or minority logic gate with non-linear input capacitors without reset

Dual hydrogen barrier layer for trench capacitors integrated with low density film for logic structures

Multi-element gain memory bit-cell having stacked and folded planar memory elements with and without offset

Dual hydrogen barrier layer for trench capacitors integrated with low density film for logic structures and methods of fabrication

Integration of ferroelectric memory devices having stacked electrodes with transistors

Computer-aided design tool for minimum gate count initialization