Inventor profile of:

Robert M. Houle

City:

Williston, Vermont

Country:

United States

Published Applications:

15

Last publication date:

2018-03-13

Top Assignees for applications by Robert M. Houle

The entities that hold a legal rights for patent applications filed by inventor Houle Robert M.:

Recent patent applications by Houle Robert M.

Robert M. Houle from Williston, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2018-03-13
US15340579
Physics

Ternary content addressable memory (TCAM) for multi bit miss detect circuit

#2 | 2017-07-13
US20170200500A1
Physics

Content-addressable memory having multiple reference matchlines to reduce latency

#3 | 2017-02-28
US15164325
Physics

Matchline precharge architecture for self-reference matchline sensing

#4 | 2015-01-22
US20150025857A1
Physics

STATISTICAL POWER ESTIMATION

#5 | 2013-11-21
US20130307580A1
Electricity

Majority dominant power scheme for repeated structures and structures thereof

#6 | 2013-09-12
US20130234754A1
Electricity

Majority dominant power scheme for repeated structures and structures thereof

#7 | 2013-06-13
US20130148455A1
Physics

Fine granularity power gating

#8 | 2012-03-29
US20120075919A1
Physics

Methods and systems for adjusting wordline up-level voltage to improve production yield relative to SRAM-cell stability

#9 | 2012-03-29
US20120075918A1
Physics

SRAM having wordline up-level voltage adjustable to assist bitcell stability and design structure for same

#10 | 2011-04-21
US20110090750A1
Physics

SRAM delay circuit that tracks bitcell characteristics

#11 | 2010-12-16
US20100315894A1
Physics

Method for low power sensing in a multi-port SRAM using pre-discharged bit lines

#12 | 2010-12-09
US20100309740A1
Physics

Low power, single-ended sensing in a multi-port SRAM using pre-discharged bit lines

#13 | 2009-06-04
US20090144507A1
Physics

APPARATUS AND METHOD FOR IMPLEMENTING REFRESHLESS SINGLE TRANSISTOR CELL eDRAM FOR HIGH PERFORMANCE MEMORY APPLICATIONS

#14 | 2009-06-04
US20090144504A1
Physics

STRUCTURE FOR IMPLEMENTING REFRESHLESS SINGLE TRANSISTOR CELL eDRAM FOR HIGH PERFORMANCE MEMORY APPLICATIONS

#15 | 2005-08-18
US20050180228A1
Physics

Method and circuit for dynamic read margin control of a memory array

InventorID:

284110 ⎘