Beijing
China
19
2020-04-14
The entities that hold a legal rights for patent applications filed by inventor Wang Runsheng:
Runsheng Wang from Beijing, CN has applied for patents for these inventions. The list has both pending applications and granted patents:
Method of bias temperature instability calculation and prediction for MOSFET and FinFET
#2 | 2016-06-02METHOD FOR EXTRACTING TRAP TIME CONSTANT OF GATE DIELECTRIC LAYER IN SEMICONDUCTOR DEVICE
#3 | 2015-08-20Method for fabricating FinFET with separated double gates on bulk silicon
#4 | 2015-05-21METHOD FOR FABRICATING FINFET ON GERMANIUM OR GROUP III-V SEMICONDUCTOR SUBSTRATE
#5 | 2013-08-22Method for testing density and location of gate dielectric layer trap of semiconductor device
#6 | 2013-07-04Field effect transistor with a vertical channel and fabrication method thereof
#7 | 2013-05-23METHOD FOR FABRICATING ULTRA-FINE NANOWIRE
#8 | 2013-03-28Programmable array of silicon nanowire field effect transistor and method for fabricating the same
#9 | 2013-02-12Method for fabricating ultra-fine nanowire
#10 | 2013-01-17Fabrication method for surrounding gate silicon nanowire transistor with air as spacers
#11 | 2013-01-10Fabrication method of vertical silicon nanowire field effect transistor
#12 | 2012-11-29Method for fabricating silicon nanowire field effect transistor based on wet etching
#13 | 2012-11-29Method for fabricating surrounding-gate silicon nanowire transistor with air sidewalls
#14 | 2012-10-18SURFACE TREATMENT METHOD FOR GERMANIUM BASED DEVICE
#15 | 2012-09-20METHOD FOR FABRICATING FINE LINE
#16 | 2012-08-09High voltage-resistant lateral double-diffused transistor based on nanowire device
#17 | 2012-07-26Method for fabricating semiconductor nano circular ring
#18 | 2012-07-26Method for testing trap density of gate dielectric layer in semiconductor device having no substrate contact
#19 | 2012-05-10Method for fabricating a tunneling field-effect transistor
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