Kaushik A. Kumar

On-chip cooling for integrated circuits

On-chip cooling systems for integrated circuits

Metal interconnect and IC chip including metal interconnect

Method for fabricating a semiconductor structure

SELF-ASSEMBLED MATERIAL PATTERN TRANSFER CONTRAST ENHANCEMENT

Thermal gradient control of high aspect ratio etching and deposition processes

On-chip cooling systems for integrated circuits

METHOD OF MINIMIZING VIA SIDEWALL DAMAGES DURING DUAL DAMASCENE TRENCH REACTIVE ION ETCHING IN A VIA FIRST SCHEME

Structures and methods for reduction of parasitic capacitances in semiconductor integrated circuits

Method for forming conductive structures

MANUFACTURING IC CHIP IN PORTIONS FOR LATER COMBINING, AND RELATED STRUCTURE

Metal interconnect forming methods and IC chip including metal interconnect

Damascene wiring fabrication methods incorporating dielectric cap etch process with hard mask retention

Sidewall semiconductor transistors

Polycarbosilane buried etch stops in interconnect structures

STRUCTURE FOR REDUCING LATERAL FRINGE CAPACITANCE IN SEMICONDUCTOR DEVICES

Dual damascene integration of ultra low dielectric constant porous materials

Field effect transistors (FETS) with inverted source/drain metallic contacts, and method of fabrication same

Method of forming a structure for reducing lateral fringe capacitance in semiconductor devices

MOSFET WTH HIGH ANGLE SIDEWALL GATE AND CONTACTS FOR REDUCED MILLER CAPACITANCE

Polycarbosilane buried etch stops in interconnect structures

Field effect transistors (FETS) with inverted source/drain metallic contacts, and method of fabricating same

Post-etch removal of fluorocarbon-based residues from a hybrid dielectric structure

MOSFET with high angle sidewall gate and contacts for reduced miller capacitance

Polycarbosilane buried etch stops in interconnect structures

DETECTION OF LOSS OF PLASMA CONFINEMENT

Back end interconnect with a shaped interface

Sidewall semiconductor transistors

Method for dual damascene integration of ultra low dielectric constant porous materials

Lowered Source/Drain Transistors

De-fluorination of wafer surface and related structure

OXIDIZED TANTALUM NITRIDE AS AN IMPROVED HARDMASK IN DUAL-DAMASCENE PROCESSING

Back end interconnect with a shaped interface

Crystallographic modification of hard mask properties

Photoresist ash process with reduced inter-level dielectric ( ILD) damage

Method for reactive ion etch processing of a dual damascene structure

Plasma surface modification and passivation of organo-silicate glass films for improved hardmask adhesion and optimal RIE processing

Dual damascene integration of ultra low dielectric constant porous materials