Alexandre E. Eichenberger

Dedicated memory structure holding data for detecting available worker thread(s) and informing available worker thread(s) of task(s) to execute

Optimizing branch re-wiring in a software instruction cache

Adaptive runtime for a multiprocessing API

Adaptive runtime for a multiprocessing API

Schedulers with load-store queue awareness

Schedulers with load-store queue awareness

Program structure-based blocking

Program structure-based blocking

Thread Specific Compiler Generated Customization of Runtime Support for Application Programming Interfaces

SIMD compare instruction using permute logic for distributed register files

Efficient Enqueuing of Values in SIMD Engines with Permute Unit

Write-through cache optimized for dependence-free parallel regions

Optimized scalar promotion with load and splat SIMD instructions

Constant time worker thread allocation via configuration caching

Write-through cache optimized for dependence-free parallel regions

Runtime dependence-aware scheduling using assist thread

Runtime extraction of data parallelism

Parallel execution unit that extracts data parallelism at runtime

Data parallel function call for determining if called routine is data parallel

Vector Loads from Scattered Memory Locations

Vector loads with multiple vector elements from a same cache line in a scattered load operation

Matrix multiplication operations using pair-wise load and splat operations

Reducing parallelism of computer source code

Shared prefetching to reduce execution skew in multi-threaded systems

Building approximate data dependences with a moving window

Runtime extraction of data parallelism

Parallel execution unit that extracts data parallelism at runtime

Data parallel function call for determining if called routine is data parallel

Method and structure of using SIMD vector architectures to implement matrix multiplication

Tracking and detecting thread dependencies using speculative versioning cache

Version pressure feedback mechanisms for speculative versioning caches

Insertion of operation-and-indicate instructions for optimized SIMD code

In-Data Path Tracking of Floating Point Exceptions and Store-Based Exception Indication

Checkpointing in speculative versioning caches

Complex matrix multiplication operations with data pre-conditioning in a high performance computing architecture

Matrix multiplication operations with data pre-conditioning in a high performance computing architecture

Runtime dependence-aware scheduling using assist thread

All-to-all permutation of vector elements based on a permutation pattern encoded in mantissa and exponent bits in a floating-point SIMD architecture

Aligning precision converted vector data using mask indicating offset relative to element boundary corresponding to precision type

Optimized code generation targeting a high locality software cache

Efficient software cache accessing with handle reuse

Single instruction multiple data (SIMD) code generation for parallel loops using versioning and scheduling

Domain stretching for an advanced dual-representation polyhedral loop transformation framework

Optimized scalar promotion with load and splat SIMD instructions

Data transfer optimized software cache for irregular memory references

Data transfer optimized software cache for regular memory references

Method using SLP packing with statements having both isomorphic and non-isomorphic expressions

SIMD code generation for loops with mixed data lengths

METHOD AND APPARATUS FOR ALLOCATING ARCHITECTURAL REGISTER RESOURCES AMONG THREADS IN A MULTI-THREADED MICROPROCESSOR CORE

System and method for advanced polyhedral loop transformations of source code in a compiler

Stable transitions in the presence of conditionals for an advanced dual-representation polyhedral loop transformation framework

Selective code generation optimization for an advanced dual-representation polyhedral loop transformation framework

INCREASE THE COVERAGE OF PROFILING FEEDBACK WITH DATA FLOW ANALYSIS

Systems, methods and computer products for cross-thread scheduling

SIMD code generation in the presence of optimized misaligned data reorganization

Efficient code generation using loop peeling for SIMD loop code with multile misaligned statements

Optimizing scalar code executed on a SIMD engine by alignment of SIMD slots

Efficient data reorganization to satisfy data alignment constraints

Method to exploit superword-level parallelism using semi-isomorphic packing

Generating optimized SIMD code in the presence of data dependences

Code generation for complex arithmetic reduction for architectures lacking cross data-path support

Workload partitioning in a parallel system with hetergeneous alignment constraints

Method and apparatus for data stream alignment support

Optimized software cache lookup for SIMD architectures

Method to efficiently prefetch and batch compiler-assisted software cache accesses

Framework for integrated intra- and inter-loop aggregation of contiguous memory accesses for SIMD vectorization

Efficient generation of SIMD code in presence of multi-threading and other false sharing conditions and in machines having memory protection support

Method for improving processing of relatively aligned memory references for increased reuse opportunities

Analyze and reduce number of data reordering operations in SIMD code

Apparatus and method for optimizing scalar code executed on a SIMD engine by alignment of SIMD slots

Method and system for versioning codes based on relative alignment for single instruction multiple data units

Method and system for data-driven runtime alignment operation

Framework for integrated intra- and inter-loop aggregation of contiguous memory accesses for SIMD vectorization

SIMD code generation in the presence of optimized misaligned data reorganization

Framework for efficient code generation using loop peeling for SIMD loop code with multiple misaligned statements

Efficient data reorganization to satisfy data alignment constraints

SIMD code generation for loops with mixed data lengths

Framework for generating mixed-mode operations in loop-level simdization

Method and apparatus for eliminating the need for register assignment, allocation, spilling and re-filling