Inventor profile of:

John S. Dodson

City:

Austin, Texas

Country:

United States

Published Applications:

33

Last publication date:

2019-08-15

Top Assignees for applications by John S. Dodson

The entities that hold a legal rights for patent applications filed by inventor Dodson John S.:

Recent patent applications by Dodson John S.

John S. Dodson from Austin, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2019-08-15
US20190250682A1
Physics

Scalable data collection for system management

#2 | 2019-08-08
US20190244676A1
Physics

Performing error correction in computer memory

#3 | 2019-07-18
US20190221280A1
Physics

Tracking address ranges for computer memory errors

#4 | 2018-05-03
US20180121375A1
Physics

Dynamically adjusting read data return sizes based on interconnect bus utilization

#5 | 2018-03-08
US20180068741A1
Physics

Tracking address ranges for computer memory errors

#6 | 2018-03-08
US20180067806A1
Physics

Confirming memory marks indicating an error in computer memory

#7 | 2018-03-08
US20180067798A1
Physics

Performing error correction in computer memory

#8 | 2018-03-08
US20180067719A1
Physics

Managing entries in a mark table of computer memory errors

#9 | 2018-02-13
US15339465
Physics

Dynamically adjusting read data return sizes based on interconnect bus utilization

#10 | 2017-06-20
US15339406
Physics

Dynamically adjusting read data return sizes based on memory interface bus utilization

#11 | 2016-12-22
US20160371159A1
Physics

Synchronization and order detection in a memory system

#12 | 2016-12-15
US20160364303A1
Physics

Reestablishing synchronization in a memory system

#13 | 2016-10-27
US20160314072A1
Physics

Probabilistic associative cache

#14 | 2016-06-30
US20160188423A1
Physics

Synchronization and order detection in a memory system

#15 | 2016-06-30
US20160188398A1
Physics

Reestablishing synchronization in a memory system

#16 | 2016-05-12
US20160132085A1
Physics

Scalable data collection for system management

#17 | 2015-03-26
US20150089279A1
Physics

Implementing memory module communications with a host processor in multiported memory configurations

#18 | 2015-01-15
US20150019831A1
Physics

Dual asynchronous and synchronous memory system

#19 | 2014-10-16
US20140310478A1
Physics

Modification of prefetch depth based on high latency event

#20 | 2014-10-16
US20140310477A1
Physics

Modification of prefetch depth based on high latency event

#21 | 2014-10-09
US20140304573A1
Physics

Transient condition management utilizing a posted error detection processing protocol

#22 | 2014-10-09
US20140304558A1
Physics

Transient condition management utilizing a posted error detection processing protocol

#23 | 2014-09-18
US20140281783A1
Electricity

Replay suspension in a memory system

#24 | 2014-09-18
US20140281653A1
Physics

Reestablishing synchronization in a memory system

#25 | 2014-09-18
US20140281326A1
Physics

Dual asynchronous and synchronous memory system

#26 | 2014-09-18
US20140281325A1
Physics

Synchronization and order detection in a memory system

#27 | 2014-05-29
US20140149751A1
Physics

Scalable data collection for system management

#28 | 2014-05-22
US20140143613A1
Physics

Selective posted data error detection based on request type

#29 | 2014-05-22
US20140143611A1
Physics

Selective posted data error detection based on request type

#30 | 2014-03-20
US20140082272A1
Physics

Memory reorder queue biasing preceding high latency operations

#31 | 2013-11-07
US20130297879A1
Physics

Probabilistic associative cache

#32 | 2013-08-15
US20130212330A1
Physics

Memory reorder queue biasing preceding high latency operations

#33 | 2013-06-13
US20130151867A1
Physics

Synchronized command throttling for multi-channel duty-cycle based memory power management

InventorID:

290667 ⎘