Inventor profile of:

Chun-Lien SU

City:

Taichung

Country:

Taiwan

Published Applications:

19

Last publication date:

2025-08-07

Top Assignees for applications by Chun-Lien SU

The entities that hold a legal rights for patent applications filed by inventor SU Chun-Lien:

Recent patent applications by SU Chun-Lien

Chun-Lien SU from Taichung, TW has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2025-08-07
US20250252042A1
Physics

MANAGING LOGIC UNITS OF MEMORY DEVICES

#2 | 2025-03-20
US20250095751A1
Physics

MANAGING POWER SUPPLY IN SEMICONDUCTOR DEVICES

#3 | 2024-04-04
US20240111527A1
Physics

Managing status information of logic units

#4 | 2023-08-03
US20230244500A1
Physics

Serial NAND flash with XIP capability

#5 | 2023-01-05
US20230004649A1
Physics

Memory device having safety boot capability

#6 | 2022-12-08
US20220392562A1
Physics

AUTOMATICALLY SKIP BAD BLOCK IN CONTINUOUS READ OR SEQUENTIAL CACHE READ OPERATION

#7 | 2022-08-25
US20220269606A1
Physics

File system management in memory device

#8 | 2022-08-25
US20220269513A1
Physics

Serial NAND flash with XiP capability

#9 | 2022-06-16
US20220188238A1
Physics

Flash memory system and flash memory device thereof

#10 | 2022-06-09
US20220180961A1
Physics

Memory device and read method thereof

#11 | 2022-05-05
US20220138109A1
Physics

Continuous read with multiple read commands

#12 | 2021-09-30
US20210304827A1
Physics

Memory system and method capable of performing wear leveling

#13 | 2021-09-09
US20210279172A1
Physics

Continuous read with multiple read commands

#14 | 2021-07-27
US16841711
Physics

Non-volatile register and implementation of non-volatile register

#15 | 2021-02-18
US20210049309A1
Physics

Secure memory

#16 | 2020-12-17
US20200396054A1
Electricity

Secure Memory Read

#17 | 2020-12-10
US20200387454A1
Physics

Memory device, electronic device, and associated read method

#18 | 2020-11-26
US20200371703A1
Physics

Data transfer between memory devices on shared bus

#19 | 2020-10-29
US20200341652A1
Physics

Input/output delay optimization method, electronic system and memory device using the same

InventorID:

2918113 ⎘