Ottawa
Canada
35
2026-04-16
The entities that hold a legal rights for patent applications filed by inventor Jain Sanjeev Kumar:
Sanjeev Kumar Jain from Ottawa, CA has applied for patents for these inventions. The list has both pending applications and granted patents:
Systems and Methods for a Power Wake-Up Sequence In a Memory Device
#2 | 2025-10-16Systems and Methods for Controlling Power Assertion In a Memory Device
#3 | 2025-08-14Bit Line Pre-Charge Circuit for Power Management Modes in Multi Bank SRAM
#4 | 2025-06-12Write Driver Boost Circuit for Memory Cells
#5 | 2025-02-20Circuitry for Power Management Assertion
#6 | 2025-02-20Systems and Methods for Controlling Power Management Operations in a Memory Device
#7 | 2025-01-02MEMORY DEVICE AND DATA LATCHING METHOD
#8 | 2024-12-05Systems and Methods for a Power Wake-Up Sequence In a Memory Device
#9 | 2024-07-18Bit Line Pre-Charge Circuit for Power Management Modes in Multi Bank SRAM
#10 | 2024-05-09Systems and Methods for Controlling Power Assertion In a Memory Device
#11 | 2024-04-25Write driver boost circuit for memory cells
#12 | 2024-02-29Systems and Methods for Improved Data Access Speed
#13 | 2024-02-29Memory Circuit Including an Array Control Inhibitor
#14 | 2023-11-30Systems and methods for controlling power management operations in a memory device
#15 | 2023-10-12Low Power Scheme for Power Down in Integrated Dual Rail SRAMs
#16 | 2023-09-21Circuitry for power management assertion
#17 | 2023-07-13Bit line pre-charge circuit for power management modes in multi bank SRAM
#18 | 2022-10-20Circuitry for power management assertion
#19 | 2022-10-13Memory circuit including an array control inhibitor
#20 | 2022-10-06Systems and methods for controlling power assertion in a memory device
#21 | 2022-10-06Low power scheme for power down in integrated dual rail SRAMs
#22 | 2022-08-18Write driver boost circuit for memory cells
#23 | 2022-07-28Systems and methods for controlling power management operations in a memory device
#24 | 2022-05-05Memory device
#25 | 2022-04-28Bit line pre-charge circuit for power management modes in multi bank SRAM
#26 | 2022-03-24Write driver boost circuit for memory cells
#27 | 2022-03-03Systems and methods for improved data access speed
#28 | 2022-03-03Systems and methods for controlling power assertion in a memory device
#29 | 2022-03-03Systems and methods for controlling power management operations in a memory device
#30 | 2021-11-02Memory architecture
#31 | 2021-08-12Word line driver for low voltage operation
#32 | 2021-08-05Memory device and power management method using the same
#33 | 2021-07-01Memory circuit including an array control inhibitor
#34 | 2020-12-17Memory power management
#35 | 2019-10-24Memory device and compensation method therein
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