Williston, Vermont
United States
37
2019-03-14
The entities that hold a legal rights for patent applications filed by inventor COLLINS David S.:
David S. COLLINS from Williston, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry
#2 | 2018-02-08Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry
#3 | 2016-09-15Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry
#4 | 2016-05-05Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry
#5 | 2014-12-18Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry
#6 | 2013-06-20Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry
#7 | 2012-03-15Semiconductor structure having vias and high density capacitors
#8 | 2011-08-18Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry
#9 | 2011-07-28Metal wiring structure for integration with through substrate vias
#10 | 2011-06-23Asymmetric junction field effect transistor
#11 | 2011-01-27Method and structures for improving substrate loss and linearity in SOI substrates
#12 | 2010-11-04Lateral passive device having dual annular electrodes
#13 | 2010-10-21Metal fill structures for reducing parasitic capacitance
#14 | 2010-09-16SOI (silicon on insulator) substrate improvements
#15 | 2010-08-19Asymmetric junction field effect transistor
#16 | 2010-06-24Deep trench varactors
#17 | 2010-05-13Optimized device isolation
#18 | 2010-02-18Structure, design structure and method of manufacturing a structure having VIAS and high density capacitors
#19 | 2010-02-18Structure, design structure and method of manufacturing a structure having VIAS and high density capacitors
#20 | 2010-02-11Metal wiring structure for integration with through substrate vias
#21 | 2010-02-11Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry
#22 | 2009-07-02DESIGN METHODOLOGY FOR GUARD RING DESIGN RESISTANCE OPTIMIZATION FOR LATCHUP PREVENTION
#23 | 2009-06-18Latchup robust array I/O using through wafer via
#24 | 2009-06-18Structure for a latchup robust gate array using through wafer via
#25 | 2009-06-18Structure for a latchup robust array I/O using through wafer via
#26 | 2009-04-23Design structure incorporating semiconductor device structures that shield a bond pad from electrical noise
#27 | 2009-03-03Latchup robust gate array using through wafer via
#28 | 2009-01-22SEMICONDUCTOR DEVICE STRUCTURES AND METHODS FOR SHIELDING A BOND PAD FROM ELECTRICAL NOISE
#29 | 2008-10-30STRUCTURE AND METHOD FOR ENHANCED TRIPLE WELL LATCHUP ROBUSTNESS
#30 | 2008-06-26METAL-OXIDE-SEMICONDUCTOR (MOS) VARACTORS AND METHODS OF FORMING MOS VARACTORS
#31 | 2008-06-19SYMMETRIC CAPACITOR STRUCTURE
#32 | 2008-06-05Design methodology of guard ring design resistance optimization for latchup prevention
#33 | 2007-12-06Method for symmetric capacitor formation
#34 | 2007-12-06Lateral passive device having dual annular electrodes
#35 | 2007-09-06METHOD AND STRUCTURE OF REFRACTORY METAL REACH THROUGH IN BIPOLAR TRANSISTOR
#36 | 2007-07-26Structure and method for enhanced triple well latchup robustness
#37 | 2005-05-12ESD design, verification and checking system and method of use
294345 ⎘