Inventor profile of:

Jui-Pin Hung

City:

Hsinchu

Country:

Taiwan

Published Applications:

86

Last publication date:

2025-05-15

Top Assignees for applications by Jui-Pin Hung

The entities that hold a legal rights for patent applications filed by inventor Hung Jui-Pin:

Recent patent applications by Hung Jui-Pin

Jui-Pin Hung from Hsinchu, TW has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2025-05-15
US20250159812A1
Electricity

INTEGRATED CIRCUIT STRUCTURE

#2 | 2022-07-07
US20220217847A1
Electricity

Integrated circuit structure

#3 | 2022-05-26
US20220165587A1
Electricity

Integrated passive device package and methods of forming same

#4 | 2021-11-11
US20210351173A1
Electricity

Integrated circuit structure and method for reducing polymer layer delamination

#5 | 2021-09-09
US20210280528A1
Electricity

Semiconductor structure

#6 | 2021-07-15
US20210217726A1
Electricity

Chip on Package Structure and Method

#7 | 2020-12-03
US20200381407A1
Electricity

Structure and formation method for chip package

#8 | 2020-11-26
US20200373278A1
Electricity

Semiconductor package

#9 | 2020-11-05
US20200350279A1
Electricity

Integrated fan-out package structures with recesses in molding compound

#10 | 2020-10-01
US20200312791A1
Electricity

Packaged semiconductor devices, methods of packaging semiconductor devices, and PoP devices

#11 | 2020-09-17
US20200294936A1
Electricity

Semiconductor package

#12 | 2020-08-13
US20200258849A1
Electricity

Method for manufacturing semiconductor package structure

#13 | 2020-07-30
US20200243460A1
Electricity

Semiconductor structure

#14 | 2020-05-07
US20200144202A1
Electricity

Packaged semiconductor devices, methods of packaging semiconductor devices, and PoP devices

#15 | 2020-04-30
US20200135694A1
Electricity

Three-layer package-on-package structure and method forming same

#16 | 2020-03-19
US20200090955A1
Electricity

Integrated passive device package and methods of forming same

#17 | 2020-03-12
US20200083145A1
Electricity

Interconnect structure for package-on-package devices

#18 | 2020-02-06
US20200043900A1
Electricity

Manufacturing method of semiconductor package

#19 | 2019-11-14
US20190350082A1
Electricity

Integrated circuit structure

#20 | 2019-08-15
US20190252329A1
Electricity

Semiconductor package

#21 | 2019-08-15
US20190252296A1
Electricity

Interconnect structure for package-on-package devices

#22 | 2019-05-16
US20190148347A1
Electricity

Semiconductor structure and manufacturing method thereof

#23 | 2019-05-09
US20190139922A1
Electricity

Multi-chip package and method of formation

#24 | 2019-04-25
US20190122929A1
Electricity

Methods of packaging semiconductor devices including placing semiconductor devices into die caves

#25 | 2019-04-11
US20190109118A1
Electricity

Multi-chip fan out package and methods of forming the same

#26 | 2019-04-04
US20190103382A1
Electricity

Manufacturing method of semiconductor package

#27 | 2019-01-03
US20190006332A1
Electricity

Structure and formation method for chip package

#28 | 2018-12-27
US20180374822A1
Electricity

Chip on package structure and method

#29 | 2018-12-06
US20180350786A1
Electricity

Semiconductor package and manufacturing method of the same

#30 | 2018-12-06
US20180350770A1
Electricity

Integrated fan-out package structures with recesses in molding compound

#31 | 2018-12-06
US20180350756A1
Electricity

Packaged semiconductor devices, methods of packaging semiconductor devices, and PoP devices

#32 | 2018-12-06
US20180350678A1
Electricity

Method of manufacturing a semiconductor device including through silicon plugs

#33 | 2018-11-15
US20180331048A1
Electricity

Semiconductor structure and manufacturing method thereof

#34 | 2018-10-11
US20180294237A1
Electricity

Semiconductor package structure

#35 | 2018-10-04
US20180286839A1
Electricity

Integrated fan-out structure with guiding trenches in buffer layer

#36 | 2018-09-20
US20180269189A1
Electricity

Semiconductor structure and manufacturing method thereof

#37 | 2018-09-20
US20180269124A1
Electricity

Semiconductor package device

#38 | 2018-08-30
US20180247900A1
Electricity

Semiconductor package

#39 | 2018-08-09
US20180226378A1
Electricity

Three-layer package-on-package structure and method forming same

#40 | 2018-07-26
US20180211901A1
Electricity

Interconnect structure for package-on-package devices

#41 | 2018-07-12
US20180197755A1
Electricity

Integrated passive device package and methods of forming same

#42 | 2018-02-01
US20180033770A1
Electricity

Semiconductor package structure

#43 | 2018-01-25
US20180025992A1
Electricity

Semiconductor package structure and manufacturing method thereof

#44 | 2017-12-28
US20170373039A1
Electricity

Semiconductor package and manufacturing method of the same

#45 | 2017-12-21
US20170365587A1
Electricity

Semiconductor package and manufacturing method of the same

#46 | 2017-11-30
US20170345804A1
Electricity

Semiconductor structure and manufacturing method thereof

#47 | 2017-10-26
US20170309596A1
Electricity

Chip on package structure and method

#48 | 2017-10-12
US20170294409A1
Electricity

Multi-chip fan out package and methods of forming the same

#49 | 2017-09-28
US20170278723A1
Electricity

Molding wafer chamber

#50 | 2017-09-21
US20170271311A1
Electricity

Package on package (PoP) bonding structures

#51 | 2017-09-21
US20170271209A1
Electricity

Methods of packaging semiconductor devices including placing semiconductor devices into die caves

#52 | 2017-08-10
US20170229433A1
Electricity

Integrated fan-out structure with guiding trenches in buffer layer

#53 | 2017-08-10
US20170229432A1
Electricity

Die package with openings surrounding end-portions of through package vias (TPVs) and package on package (PoP) using the die package

#54 | 2017-06-29
US20170186736A1
Electricity

Structure and formation method for chip package

#55 | 2017-06-15
US20170170161A1
Electricity

Integrated circuit structure and method for reducing polymer layer delamination

#56 | 2017-03-14
US14881840
Electricity

Structure and formation method for chip package

#57 | 2017-01-12
US20170011981A1
Electricity

Semiconductor package device and manufacturing method thereof

#58 | 2016-11-17
US20160336280A1
Electricity

Method of forming a semiconductor package

#59 | 2016-09-15
US20160268214A1
Electricity

Semiconductor packaging structure and manufacturing method thereof

#60 | 2016-09-01
US20160254229A1
Electricity

Semiconductor structure and manufacturing method thereof

#61 | 2016-07-07
US20160197014A1
Electricity

Method of manufacturing a semiconductor device including through silicon plugs

#62 | 2016-04-28
US20160118301A1
Electricity

Package with metal-insulator-metal capacitor and method of manufacturing the same

#63 | 2015-07-02
US20150187605A1
Electricity

Method of packaging a semiconductor device

#64 | 2015-05-28
US20150147834A1
Electricity

NOVEL SEMICONDUCTOR PACKAGE WITH THROUGH SILICON VIAS

#65 | 2015-05-21
US20150137351A1
Electricity

Semiconductor device and manufacturing method thereof

#66 | 2015-04-23
US20150108634A1
Electricity

Semiconductor package device and manufacturing method thereof

#67 | 2015-04-16
US20150102503A1
Electricity

Fan out package, semiconductor device and manufacturing method thereof

#68 | 2015-01-15
US20150017764A1
Electricity

Method of forming a semiconductor package

#69 | 2015-01-08
US20150008587A1
Electricity

Semiconductor device and manufacturing method thereof

#70 | 2015-01-08
US20150008586A1
Electricity

Semiconductor device and manufacturing method thereof

#71 | 2014-08-14
US20140225222A1
Electricity

Package with metal-insulator-metal capacitor and method of manufacturing the same

#72 | 2014-07-17
US20140197535A1
Electricity

Wafer-level packaging mechanisms

#73 | 2014-03-06
US20140061888A1
Electricity

Three dimensional (3D) fan-out packaging mechanisms

#74 | 2013-11-21
US20130307143A1
Electricity

Wafer-level packaging mechanisms

#75 | 2013-11-14
US20130302979A1
Electricity

Method of manufacturing a semiconductor device including through silicon plugs

#76 | 2013-09-19
US20130244378A1
Electricity

Underfill curing method using carrier

#77 | 2013-07-04
US20130168848A1
Electricity

Packaged semiconductor device with a molding compound and a method of forming the same

#78 | 2013-06-20
US20130157412A1
Electricity

Chip on wafer bonder

#79 | 2013-05-16
US20130119533A1
Electricity

Package for three dimensional integrated circuit

#80 | 2011-10-06
US20110241061A1
Electricity

Heat dissipation by through silicon plugs

#81 | 2011-10-06
US20110241040A1
Electricity

Semiconductor package with through silicon vias

#82 | 2009-12-24
US20090317214A1
Electricity

Wafer's ambiance control

#83 | 2009-06-04
US20090142903A1
Electricity

Chip on wafer bonder

#84 | 2008-12-04
US20080298933A1
Electricity

Substrate carrier, port apparatus and facility interface and apparatus including same

#85 | 2008-12-04
US20080295412A1
Electricity

Apparatus for storing substrates

#86 | 2007-10-11
US20070235662A1
Electricity

Flash lamp annealing device

InventorID:

300053 ⎘