Michael B. Spear

Calibrating a quadrature receive serial interface

Low-latency deserializer having fine granularity and defective-lane compensation

Reducing latency of memory read operations returning data on a read data path across multiple clock boundaries, to a host implementing a high speed serial interface

Built-in self-test for receiver channel

Reducing chip latency at a clock boundary by reference clock phase adjustment

Reducing latency of memory read operations returning data on a read data path across multiple clock boundaries, to a host implementing a high speed serial interface

Double data rate (DDR) memory read latency reduction

Staged power on/off sequence at the I/O phy level in an interchip interface

Power reduction in a parallel data communications interface using clock resynchronization

Power reduction in a parallel data communications interface using clock resynchronization

System and method to inject a bit error on a bus lane

Communicating Control Information for a Data Communications Link Via a Line Being Calibrated

Parallel data communications mechanism having reduced power continuously calibrated lines

Dynamic fault detection and repair in a data communications mechanism

Calibration of multiple parallel data communications lines for high skew conditions

Coordinating Communications Interface Activities in Data Communicating Devices Using Redundant Lines

Power-on initialization and test for a cascade interconnect memory system

Arrangements for Operating In-Line Memory Module Configurations

Combined alignment scrambler function for elastic interface

Combined alignment scrambler function for elastic interface