Inventor profile of:

Jian Chen

City:

Austin, Texas

Country:

United States

Published Applications:

17

Last publication date:

2013-01-22

Top Assignees for applications by Jian Chen

The entities that hold a legal rights for patent applications filed by inventor Chen Jian:

Recent patent applications by Chen Jian

Jian Chen from Austin, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2013-01-22
US12557737
-

Workload-guided application scheduling in multi-core system based at least on applicaton branch transition rates

#2 | 2012-01-05
US20120003802A1
Electricity

Transistor with asymmetric silicon germanium source region

#3 | 2011-10-11
US11278618
-

Transistor with asymmetric silicon germanium source region

#4 | 2011-05-17
US11383295
-

Diode with asymmetric silicon germanium anode

#5 | 2008-05-01
US20080104550A1
Physics

Compensating for layout dimension effects in semiconductor device modeling

#6 | 2008-01-03
US20080003789A1
Electricity

Providing stress uniformity in a semiconductor device

#7 | 2007-05-03
US20070099361A1
Electricity

Method for forming a semiconductor structure and structure thereof

#8 | 2007-05-03
US20070099353A1
Electricity

Method for forming a planar and vertical semiconductor structure having a strained semiconductor layer

#9 | 2006-07-20
US20060157783A1
Electricity

Semiconductor device having trench isolation for differential stress and method therefor

#10 | 2006-05-04
US20060091461A1
Electricity

Transistor structure with dual trench for optimized stress effect and method therefor

#11 | 2006-04-06
US20060073698A1
Electricity

Plasma enhanced nitride layer

#12 | 2006-03-02
US20060043500A1
Electricity

Transistor structure with stress modification and capacitive reduction feature in a channel direction and method thereof

#13 | 2006-03-02
US20060043422A1
Electricity

Transistor structure with stress modification and capacitive reduction feature in a width direction and method thereof

#14 | 2006-01-19
US20060011988A1
Electricity

Integrated circuit with multiple spacer insulating region widths

#15 | 2005-11-10
US20050250287A1
Electricity

Method of semiconductor fabrication incorporating disposable spacer into elevated source/drain processing

#16 | 2005-09-01
US20050190421A1
Electricity

Integrated circuit with multiple spacer insulating region widths

#17 | 2005-03-08
US10285374
-

Semiconductor fabrication process using transistor spacers of differing widths

InventorID:

3066021 ⎘