LEO MATHEW

Structures and methods of fabricating electronic devices using separation and charge depletion techniques

Structures and methods of fabricating electronic devices using separation and charge depletion techniques

METHOD OF FORMING AN ELECTRONIC DEVICE USING A SEPARATION TECHNIQUE

Phase change memory cell with heater and method therefor

Two-transistor floating-body dynamic memory cell

Integrated circuit using FinFETs and having a static random access memory (SRAM)

METHOD OF FORMING AN ELECTRONIC DEVICE USING A SEPARATION TECHNIQUE

Method of forming a finFET and structure

Method of forming an electronic device using a separation technique

Method of forming an electronic device using a separation-enhancing species

METHOD OF FORMING AN ELECTRONIC DEVICE INCLUDING REMOVING A DIFFERENTIAL ETCH LAYER

Phase change memory cell with heater and method therefor

Method of making a phase change memory cell having a silicide heater in conjunction with a FinFET

MIGFET circuit with ESD protection

Semiconductor fabrication process including silicide stringer removal processing

FinFET memory cell having a floating gate and method therefor

Multiple device types including an inverted-T channel transistor and method therefor

Electronic device including a gated diode

Method to control uniformity/composition of metal electrodes, silicides on topography and devices using this method

Method to improve source/drain parasitics in vertical devices

Method of forming a semiconductor device having a removable sidewall spacer

Process of forming an electronic device including forming a gate electrode layer and forming a patterned masking layer

Electronic device including a semiconductor fin having a plurality of gate electrodes and a process for forming the electronic device

Split game memory cell method

METHOD OF FORMING A SEMICONDUCTOR DEVICE HAVING A SYMMETRIC DIELECTRIC REGIONS AND STRUCTURE THEREOF

Light erasable memory and method therefor

Twisted dual-substrate orientation (DSO) substrates

Semiconductor structure pattern formation

Method of separating a structure in a semiconductor device

Phase detector device and method thereof

Semiconductor optical devices having fin structures

Method for forming a semiconductor-on-insulator (SOI) body-contacted device with a portion of drain region removed

Temperature compensation device and method thereof

Method of forming a semiconductor device with decreased undercutting of semiconductor material

Process for forming an electronic device including a fin-type structure

Integrated circuit using FinFETs and having a static random access memory (SRAM)

Electronic device and a process for forming the electronic device

Semiconductor optical devices and method for forming

Multiple device types including an inverted-T channel transistor and method therefor

Method of making an inverted-T channel transistor

Signal converters with multiple gate devices

Voltage controlled oscillator with a multiple gate transistor and method therefor

Semiconductor device having nano-pillars and method therefor

Multiple fin formation

Transistor with independent gate structures

Semiconductor fabrication process including silicide stringer removal processing

Integrated circuit with multiple independent gate field effect transistor (MIGFET) rail clamp circuit

Method of forming a semiconductor device having asymmetric dielectric regions and structure thereof

Process of forming a non-volatile memory cell including a capacitor structure

Vertical transistor NVM with body contact structure and method

Hybrid-FET and its application as SRAM

Asymmetric spacers and asymmetric source/drain extension layers

Semiconductor device having conductive spacers in sidewall regions and method for forming

Method of making a double gate semiconductor device with self-aligned gates and structure thereof

Transistor with vertical dielectric structure

Semiconductor optical devices and method for forming

Semiconductor fabrication process with asymmetrical conductive spacers

Transistor having multiple channels

Semiconductor fabrication process with asymmetrical conductive spacers

Method and circuit for multiplying signals with a transistor having more than one independent gate structure

Confined spacers for double gate transistor semiconductor fabrication process

Transistor having three electrically isolated electrodes and method of formation

Memory with charge storage locations and adjacent gate structures

Method of forming a transistor having multiple channels

Method for converting a planar transistor design to a vertical double gate transistor design

Method for forming a double-gated semiconductor device