Jack A. Mandelman

Sea-of-fins structure on a semiconductor substrate and method of fabrication

Structure and method for improving storage latch susceptibility to single event upsets

Trench anti-fuse structures for a programmable integrated circuit

Sea-of-fins structure on a semiconductor substrate and method of fabrication

Structure and method for improving storage latch susceptibility to single event upsets

Magnetic induction grid as an early warning mechanism for space based microelectronics

Vertical SOI trench SONOS cell

SOI field effect transistor with a back gate for modulating a floating body

Semitubular metal-oxide-semiconductor field effect transistor

Method of multi-port memory fabrication with parallel connected trench capacitors in a cell

Vertical SOI trench SONOS cell

High-density, trench-based non-volatile random access SONOS memory SOC applications

Memory elements and methods of using the same

Design structure for an automatic driver/transmission line/receiver impedance matching circuitry

Silicon on insulator devices having body-tied-to-source and methods of making

SOI CMOS compatible multiplanar capacitor

Dual port gain cell with side and top gated read transistor

Tunneling effect transistor with self-aligned gate

Thin gate electrode CMOS devices and methods of fabricating same

Method of manufacturing a body-contacted finfet

DIGITAL CIRCUITS HAVING ADDITIONAL CAPACITORS FOR ADDITIONAL STABILITY

FinFET with top body contact

Semiconductor structure for fuse and anti-fuse applications

SOI MOSFET WITH A METAL SEMICONDUCTOR ALLOY GATE-TO-BODY BRIDGE

METHOD AND APPARATUS FOR WAFER EDGE CLEANING

Ultra thin channel (UTC) MOSFET structure formed on BOX regions having different depths and different thicknesses beneath the UTC and source/drain regions and method of manufacture thereof

Silicon on insulator devices having body-tied-to-source and methods of making

Electronic fuse with conformal fuse element formed over a freestanding dielectric spacer

Silicon on insulator (SOI) field effect transistors (FETs) with adjacent body contacts

Automatic Driver/Transmission Line/Receiver Impedance Matching Circuitry

SUB-LITHOGRAPHIC FACETING FOR MOSFET PERFORMANCE ENHANCEMENT

Patterned silicon-on-insulator layers and methods for forming the same

Soft error reduction of CMOS circuits on substrates with hybrid crystal orientation using buried recombination centers

METAL-OXIDE-SEMICONDUCTOR FIELD EFFECT TRANSISTOR WITH AN ASYMMETRIC SILICIDE

High performance single event upset hardened SRAM cell

PROGRAMMABLE CAPACITORS AND METHODS OF USING THE SAME

Nano-fuse structural arrangements having blow protection barrier spaced from and surrounding fuse link

Deep junction SOI MOSFET with enhanced edge body contacts

Sub-lithographic local interconnects, and methods for forming same

Pillar P-i-n semiconductor diodes

Storage Elements with Disguised Configurations and Methods of Using the Same

Vertical SOI transistor memory cell and method of forming the same

Production of limited lifetime devices achieved through E-fuses

Mesa Optical Sensors and Methods of Manufacturing the Same

Method of fabricating high-density, trench-based non-volatile random access SONOS memory cells for SOC applications

CMOS Devices Adapted to Prevent Latchup and Methods of Manufacturing the Same

Electrically programmable π-shaped fuse structures and design process therefore

Electrically programmable fuse structures with narrowed width regions configured to enhance current crowding and methods of fabricating thereof

Coplanar silicon-on-insulator (SOI) regions of different crystal orientations and methods of making the same

Coplanar silicon-on-insulator (SOI) regions of different crystal orientations and methods of making the same

ELECTRICALLY PROGRAMMABLE PI-SHAPED FUSE STRUCTURES AND METHODS OF FABRICATION THEREOF

CMOS devices adapted to prevent latchup and methods of manufacturing the same

Mesa Optical Sensors and Methods of Manufacturing the Same

Electrically programmable π-shaped fuse structures and methods of fabrication thereof

Dual metal integration scheme based on full silicidation of the gate electrode

Real-time adaptive SRAM array for high SEU immunity

Electronic fuse with conformal fuse element formed over a freestanding dielectric spacer

Electrically programmable fuse structures with narrowed width regions configured to enhance current crowding and methods of fabrication thereof

Electrically programmable π-shaped fuse structures and methods of fabrication thereof

Electrically programmable fuse structures with terminal portions residing at different heights, and methods of fabrication thereof

Vertical SOI transistor memory cell

Method of fabricating a body capacitor for SOI memory

Memory elements and methods of using the same

Method of manufacturing a multiple port memory having a plurality of parallel connected trench capacitors in a cell

Programmable capacitors and methods of using the same

Opto-thermal mask including aligned thermal dissipative layer, reflective layer and transparent capping layer

CMOS devices adapted to reduce latchup and methods of manufacturing the same

Silicon-on-insulator (SOI) read only memory (ROM) array and method of making a SOI ROM

Vertical SOI trench SONOS cell

CMOS compatible shallow-trench efuse structure and method

Trench memory cells with buried isolation collars, and methods of fabricating same

eFuse and methods of manufacturing the same

Isolation collar void and methods of forming the same

Memory cells with planar FETs and vertical FETs with a region only in upper region of a trench and methods of making and using same

PLANAR ULTRA-THIN SEMICONDUCTOR-ON-INSULATOR CHANNEL MOSFET WITH EMBEDDED SOURCE/DRAIN

Silicon-on-insulator (SOI) Read Only Memory (ROM) array and method of making a SOI ROM

Dual port gain cell with side and top gated read transistor

Sea-of-fins structure on a semiconductor substrate and method of fabrication

Fin field effect transistors (FinFETs) and methods for making the same

Vertical MOSFET SRAM cell

Variable-gain-amplifier based limiter to remove amplitude modulation from a VCO output

Method of forming self-aligned low-k gate cap

Patterned silicon-on-insulator layers and methods for forming the same

Coplanar silicon-on-insulator (SOI) regions of different crystal orientations and methods of making the same

Lateral lubistor structure and method

Fin field effect transistors (FinFETs) and methods for making the same

Vertical MOSFET SRAM cell

Structure and method of fabricating high-density trench-based non-volatile random access SONOS memory cells for SOC applications

Body capacitor for SOI memory description

Self-aligned low-k gate cap

Trench capacitor vertical structure

Strained finFET CMOS device structures

High performance embedded DRAM technology with strained silicon

Isolation structures for imposing stress patterns

Isolation structures for imposing stress patterns

Method of creating deep trench capacitor using a P+ metal electrode

Method of making encapsulated spacers in vertical pass gate DRAM and damascene logic gates

Gate structure with independently tailored vertical doping profile

Method of creating deep trench capacitor using a P+ metal electrode

Field effect transistor with stressed channel and method for making same