Inventor profile of:

Daniel Mark Nelson

City:

Rochester, Minnesota

Country:

United States

Published Applications:

16

Last publication date:

2013-07-11

Top Assignees for applications by Daniel Mark Nelson

The entities that hold a legal rights for patent applications filed by inventor Nelson Daniel Mark:

Recent patent applications by Nelson Daniel Mark

Daniel Mark Nelson from Rochester, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2013-07-11
US20130175631A1
Electricity

Layout to minimize FET variation in small dimension photolithography

#2 | 2012-04-12
US20120087176A1
Physics

Data security for dynamic random access memory using body bias to clear data at power-up

#3 | 2012-04-05
US20120081143A1
Physics

Delay chain burn-in for increased repeatability of physically unclonable functions

#4 | 2010-08-26
US20100214859A1
Physics

Implementing boosted wordline voltage in memories

#5 | 2010-07-29
US20100188886A1
Physics

Implementing enhanced SRAM stability and enhanced chip yield with configurable wordline voltage levels

#6 | 2010-02-25
US20100046278A1
Physics

Implementing local evaluation of domino read SRAM with enhanced SRAM cell stability with minimized area usage

#7 | 2010-02-25
US20100046277A1
Physics

Implementing local evaluation of domino read SRAM with enhanced SRAM cell stability

#8 | 2010-01-28
US20100019824A1
Electricity

Low power level shifting latch circuits with gated feedback for high speed integrated circuits

#9 | 2009-12-31
US20090323445A1
Physics

High performance read bypass test for SRAM circuits

#10 | 2009-05-07
US20090116298A1
Physics

Apparatus for implementing SRAM cell write performance evaluation

#11 | 2009-03-05
US20090063912A1
Physics

Design structure embodied in a machine readable medium for implementing SRAM cell write performance evaluation

#12 | 2009-03-05
US20090059697A1
Physics

Method for implementing SRAM cell write performance evaluation

#13 | 2008-11-06
US20080273406A1
Physics

ENHANCED SRAM REDUNDANCY CIRCUIT FOR REDUCING WIRING AND REQUIRED NUMBER OF REDUNDANT ELEMENTS

#14 | 2008-05-15
US20080112237A1
Physics

Method for reducing wiring and required number of redundant elements

#15 | 2008-05-15
US20080112219A1
Physics

Method and Enhanced SRAM Redundancy Circuit for Reducing Wiring and Required Number of Redundant Elements

#16 | 2007-03-01
US20070047282A1
Physics

Method and apparatus for implementing power saving for content addressable memory

InventorID:

3135187 ⎘