Robert E. Cypher

Facilitating efficient transactional memory and atomic operations via cache line marking

Computer system with multiple classes of device IDs

Store queue supporting ordered and unordered stores

Issuing instructions with unresolved data dependencies

Memory system that provides guaranteed component-failure correction with double-error correction

Memory system that supports probalistic component-failure correction with partial-component sparing

System and method for executing a transaction using parallel co-transactions

Pre-fetching for a sibling cache

Multi-node system with global access states

Multi-node computer system with proxy transaction to read data from a non-owning memory device

Efficient interleaving between a non-power-of-two number of entities

Store queue with token to facilitate efficient thread synchronization

Mechanism for increasing parallelization in computer programs with read-after-write dependencies associated with prefix operations

Facilitating probabilistic error detection and correction after a memory component failure

Facilitating error detection and correction after a memory component failure

Supporting efficient spin-locks and other types of synchronization in a cache-coherent multiprocessor system

Hierarchical bloom filters for facilitating concurrency control

Bloom bounders for improved computer system performance

DYNAMICALLY CONFIGURING MEMORY INTERLEAVING FOR LOCALITY AND PERFORMANCE ISOLATION

Multi-node system with response information in memory

Bandwidth-efficient directory-based coherence protocol

System and method for efficient verification of memory consistency model compliance

USING TIME STAMPS TO FACILITATE LOAD REORDERING

Preventing store starvation in a system that supports marked coherence

Speculative writestream transaction

Cache-coherency protocol with held state

Store queue with store-merging and forward-progress guarantees

Method and apparatus for supporting very large transactions

Starvation-avoiding unbounded transactional memory

Deadlock avoidance during store-mark acquisition

Selectively performing lookups for cache lines

Coherence protocol with dynamic privatization

Associating data source information with runtime events

Cache line duplication in response to a way prediction conflict

Hard component failure detection and correction

Branch prediction mechanisms using multiple hash functions

Cache memory system including a partially hashed index

Computer system including network slices that map to field replaceable units

Multi-node computer system implementing global access state dependent transactions

Address packets with variable-size mask format

Computer system with multiple classes of transaction IDs

Maintaining cache coherence using load-mark metadata to deny invalidation of load-marked cache lines

Multi-node system with split ownership and access right coherence mechanism

Method and apparatus for tracking load-marks and store-marks on cache lines

Store queue architecture for a processor that supports speculative execution

Method and apparatus for implementing virtual transactional memory using cache line marking

Cache line marking with shared timestamps

Efficient marking of shared cache lines

Facilitating load reordering through cacheline marking

Facilitating store reordering through cacheline marking

Computer system implementing synchronized broadcast using timestamps

Multi-node computer system in which interfaces provide data to satisfy coherency transactions when no owning device present in modified global access state node

Multi-node system in which global address generated by processing subsystem includes global to local translation information

Efficient store queue architecture

Data corruption avoidance in DRAM chip sparing

Content-addressable memory that supports a priority ordering between banks

Content-addressable memory that supports a priority ordering between banks of differing sizes

Mechanism and method for cache snoop filtering

System and method for dynamic memory interleaving and de-interleaving

Centerplaneless computer system

Value-based memory coherence support

Method for in-place memory interleaving and de-interleaving

Multi-node computer system in which networks in different nodes implement different conveyance modes

Multiprocessing system employing address switches to control mixed broadcast snooping and directory based coherency protocols transparent to active devices

Computer system supporting read-to-write-back transactions for I/O devices

ECC for component failures using Galois fields

Instruction set architecture employing conditional multistore synchronization

Conditional synchronization mechanisms allowing multiple store operations to become visible while a flagged memory location is owned and remains unchanged

Computer system including a network employing redundant information and slicing

Cache coherence protocol with speculative writestream

Mechanism for starvation avoidance while maintaining cache consistency in computer systems

Computer system implementing synchronized broadcast using skew control and queuing

Computer system including a promise array

Mechanism and method employing a plurality of hash functions for cache snoop filtering

System and method for tolerating communication lane failures

Circuit board orientation in a computer system

Apparatus and method for determining stack distance including spatial locality of running software for estimating cache miss rates based upon contents of a hash table

Apparatus and method for determining stack distance of running software for estimating cache miss rates based upon contents of a hash table

Memory system topology

Error detection/correction code which detects and corrects a first failing component and optionally a second failing component

Memory/Transmission medium failure handling controller and method

Error detection/correction code which detects and corrects component failure and which provides single bit error correction subsequent to component failure

System with a directory based coherency protocol and split ownership and access right coherence mechanism

System with multicast invalidations and split ownership and access right coherence mechanism

System with virtual address networks and split ownership and access right coherence mechanism

Branch prediction mechanism using multiple hash functions

Mechanism for maintaining cache consistency in computer systems

Computer system employing redundant power distribution

System with arbitration scheme supporting virtual address networks and having split ownership and access right coherence mechanism

Multi-node computer system where active devices selectively initiate certain transactions using remote-type address packets

Multi-node computer system with active devices employing promise arrays for outstanding transactions

Multi-node computer system implementing memory-correctable speculative proxy transactions

Multi-node computer system employing multiple memory response states