Fishkill, New York
United States
29
2012-10-18
The entities that hold a legal rights for patent applications filed by inventor Ji Brian L.:
Brian L. Ji from Fishkill, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Switched capacitor voltage converters
#2 | 2012-07-05Voltage conversion and integrated circuits with stacked voltage domains
#3 | 2012-05-17TERNARY CONTENT ADDRESSABLE MEMORY USING PHASE CHANGE DEVICES
#4 | 2011-12-08Low voltage signaling
#5 | 2011-09-29Embedded DRAM integrated circuits with extremely thin silicon-on-insulator pass transistors
#6 | 2011-05-05TWO PFET SOI MEMORY CELLS
#7 | 2010-10-14Voltage conversion and integrated circuits with stacked voltage domains
#8 | 2010-09-09Ternary content addressable memory using phase change devices
#9 | 2010-08-26Switched capacitor voltage converters
#10 | 2010-01-07Content addressable memory using phase change devices
#11 | 2009-04-30Embedded DRAM integrated circuits with extremely thin silicon-on-insulator pass transistors
#12 | 2009-03-05Multi-port dynamic memory methods
#13 | 2008-12-04High-speed multi-mode receiver
#14 | 2008-10-16Write operations for phase-change-material memory
#15 | 2008-07-24Multi-port dynamic memory structures
#16 | 2008-06-19Methods and apparatus for inline variability measurement of integrated circuit components
#17 | 2007-06-14Methods and apparatus for inline variability measurement of integrated circuit components
#18 | 2007-05-08Content addressable memory having reduced power consumption
#19 | 2007-02-01Write operations for phase-change-material memory
#20 | 2007-01-04Non-volatile content addressable memory using phase-change-material memory elements
#21 | 2006-10-05Precision tuning of a phase-change resistive element
#22 | 2006-03-30High Speed Multi-Mode Receiver with adaptive receiver equalization and controllable transmitter pre-distortion
#23 | 2006-02-28Global planarization of wafer scale package with precision die thickness control
#24 | 2006-02-23Apparatus and method for shielding a wafer from charged particles during plasma etching
#25 | 2005-12-27Method and system for optimizing transmission and reception power levels in a communication system
#26 | 2005-10-13Destructive-read random access memory system buffered with destructive-read memory cache
#27 | 2005-09-20Destructive-read random access memory system buffered with destructive-read memory cache
#28 | 2005-05-26Adaptive data transmitter having rewriteable non-volatile storage
#29 | 2005-03-31Segmented content addressable memory architecture for improved cycle time and reduced power consumption
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