Inventor profile of:

Eric Nequist

City:

Monte Sereno, California

Country:

United States

Published Applications:

25

Last publication date:

2013-02-12

Top Assignees for applications by Eric Nequist

The entities that hold a legal rights for patent applications filed by inventor Nequist Eric:

Recent patent applications by Nequist Eric

Eric Nequist from Monte Sereno, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2013-02-12
US12987064
-

Method and mechanism for implementing extraction for an integrated circuit design

#2 | 2012-11-20
US12987072
-

Method and mechanism for implementing extraction for an integrated circuit design

#3 | 2012-05-24
US20120131524A1
Physics

Method and mechanism for identifying and tracking shape connectivity

#4 | 2012-03-13
US12648843
-

Method and mechanism for identifying and tracking shape connectivity

#5 | 2011-12-22
US20110314432A1
Physics

Method and system for implementing efficient locking to facilitate parallel processing of IC designs

#6 | 2011-06-28
US11741685
-

Method and system for implementing partial reconfiguration and rip-up of routing

#7 | 2011-04-21
US20110093826A1
Physics

Method and system for model-based routing of an integrated circuit

#8 | 2011-01-11
US11741699
-

Method and mechanism for implementing extraction for an integrated circuit design

#9 | 2010-05-25
US11678594
-

System and method for layout optimization using model-based verification

#10 | 2010-05-18
US11648128
-

Method and system for implementing edge optimization on an integrated circuit design

#11 | 2010-02-16
US11229320
-

Method and mechanism for identifying and tracking shape connectivity

#12 | 2010-02-02
US11741694
-

Method and system for implementing routing refinement and timing convergence

#13 | 2009-11-03
US11741668
-

Representation, configuration, and reconfiguration of routing method and system

#14 | 2009-09-15
US11648151
-

Method and system for implementing layout, placement, and routing with merged shapes

#15 | 2009-08-06
US20090199139A1
Physics

Method, system, and computer program product for improved electrical analysis

#16 | 2009-07-02
US20090172625A1
Physics

Method and mechanism for performing clearance-based zoning

#17 | 2009-07-02
US20090172623A1
Physics

Method and system for implementing efficient locking to facilitate parallel processing of IC designs

#18 | 2009-04-02
US20090089720A1
Physics

Method and mechanism for identifying and tracking shape connectivity

#19 | 2008-12-02
US11229344
-

Method and mechanism for determining shape connectivity

#20 | 2008-07-03
US20080163150A1
Physics

Method and system for model-based routing of an integrated circuit

#21 | 2008-07-03
US20080163134A1
Physics

Method and system for model-based design and layout of an integrated circuit

#22 | 2006-08-29
US10342862
-

Hierarchical gcell method and mechanism

#23 | 2006-08-29
US10342823
-

Zone tree method and mechanism

#24 | 2006-01-03
US10342824
-

Shape abstraction mechanism

#25 | 2005-12-27
US10342768
-

Nearest neighbor mechanism

InventorID:

3177377 ⎘