Poughkeepsie, New York
United States
28
2012-05-31
The entities that hold a legal rights for patent applications filed by inventor Vaed Kunal:
Kunal Vaed from Poughkeepsie, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Methods of fabricating passive element without planarizing and related semiconductor device
#2 | 2011-05-12METHOD OF FABRICATING A PRECISION BURIED RESISTOR
#3 | 2009-01-01Method of integration of a MIM capacitor with a lower plate of metal gate material formed on an STI region or a silicide region formed in or on the surface of a doped well with a high K dielectric material
#4 | 2008-11-27Post last wiring level inductor using patterned plate process
#5 | 2008-11-27Post last wiring level inductor using patterned plate process
#6 | 2008-11-27Post last wiring level inductor using patterned plate process
#7 | 2008-11-13Post last wiring level inductor using patterned plate process
#8 | 2008-11-06Post last wiring level inductor using patterned plate process
#9 | 2008-09-18Methods of fabricating passive element without planarizing and related semiconductor device
#10 | 2008-08-07METHOD AND STRUCTURE FOR INTEGRATING MIM CAPACITORS WITHIN DUAL DAMASCENE PROCESSING TECHNIQUES
#11 | 2008-07-24INTEGRATED CIRCUIT (IC) CHIP WITH ONE OR MORE VERTICAL PLATE CAPACITORS AND METHOD OF MAKING THE CAPACITORS
#12 | 2008-07-24Air gap under on-chip passive device
#13 | 2008-05-29Polysilicon containing resistor with enhanced sheet resistance precision and method for fabrication thereof
#14 | 2008-03-13Method and structure for integrating MIM capacitors within dual damascene processing techniques
#15 | 2008-03-06Methods of fabricating passive element without planarizing and related semiconductor device
#16 | 2008-01-03Methods of fabricating passive element without planarizing
#17 | 2007-11-29Semiconductor device structures with backside contacts for improved heat dissipation and reduced parasitic resistance
#18 | 2007-08-23Method of fabricating a precision buried resistor
#19 | 2007-07-05SINGLE OR DUAL DAMASCENE VIA LEVEL WIRINGS AND/OR DEVICES, AND METHODS OF FABRICATING SAME
#20 | 2007-03-15Integration of a MIM capacitor with a plate formed in a well region and with a high-k dielectric
#21 | 2007-02-08MOS varactor with segmented gate doping
#22 | 2007-02-01Post last wiring level inductor using patterned plate process
#23 | 2006-11-30Hi-K dielectric layer deposition methods
#24 | 2006-09-07Suspended transmission line structures in back end of line processing
#25 | 2006-01-31Damascene integration scheme for developing metal-insulator-metal capacitors
#26 | 2005-11-03Method of forming suspended transmission line structures in back end of line processing
#27 | 2005-09-06Prevention of Ta2O5 mim cap shorting in the beol anneal cycles
#28 | 2005-03-24Vertically-stacked co-planar transmission line structure for IC design
3178712 ⎘