David A. Luick

PREDICATED ISSUE FOR CONDITIONAL BRANCH INSTRUCTIONS

Cache line use history based done bit modification to D-cache replacement scheme

Cache line use history based done bit modification to I-cache replacement scheme

Cache line use history based done bit modification to D-cache replacement scheme

I-cache line use history based done bit based on successful prefetchable counter

D-cache line use history based done bit based on successful prefetchable counter

Vector morphing mechanism for multiple processor cores

Multiport execution target delay queue FIFO array

System and Method for Optimization Within a Group Priority Issue Schema for a Cascaded Pipeline

System and method for the scheduling of load instructions within a group priority issue schema for a cascaded pipeline

System and method for prioritizing branch instructions

System and method for prioritizing compare instructions

System and Method for Resolving Issue Conflicts of Load Instructions

System and method for prioritizing store instructions

System and method for prioritizing arithmetic instructions

System and Method for Prioritizing Floating-Point Instructions

System and method for optimization within a group priority issue schema for a cascaded pipeline

System and method for optimization within a group priority issue schema for a cascaded pipeline

System and Method for Resolving Issue Conflicts of Load Instructions

System and method for a group priority issue schema for a cascaded pipeline

System and Method for Issue Schema for a Cascaded Pipeline

Self prefetching L3/L4 cache mechanism

3-dimensional L2/L3 cache array to hide translation (TLB) delays

Scalar Processor Instruction Level Parallelism (ILP) Coupled Pair Morph Mechanism

Compound Instruction Group Formation and Execution

Butterfly Physical Chip Floorplan to Allow an ILP Core Polymorphism Pairing

Local and global branch prediction information storage

DESIGN STRUCTURE FOR L2 CACHE/NEST ADDRESS TRANSLATION

Minimizing unscheduled D-cache miss pipeline stalls in a cascaded delayed execution pipeline

SIMPLE LOAD AND STORE DISAMBIGUATION AND SCHEDULING AT PREDECODE

Simple load and store disambiguation and scheduling at predecode

STRUCTURE FOR EARLY CONDITIONAL BRANCH RESOLUTION

STRUCTURE FOR SELF PREFETCHING L2 CACHE MECHANISM FOR INSTRUCTION LINES

DESIGN STRUCTURE FOR DOUBLE-WIDTH INSTRUCTION QUEUE FOR INSTRUCTION EXECUTION

Scheduling instructions in a cascaded delayed execution pipeline to minimize pipeline stalls caused by a cache miss

STRUCTURE FOR A CASCADED DELAYED EXECUTION PIPELINE

DESIGN STRUCTURE FOR SELF PREFETCHING L2 CACHE MECHANISM FOR DATA LINES

Single shared instruction predecoder for supporting multiple processors

Low Cost Persistent Instruction Predecoded Issue and Dispatcher

Cascaded delayed float/vector execution pipeline

Cascaded Delayed Execution Pipeline

Store-Through L2 Cache Mode

Method and apparatus to extend the number of instruction bits in processors with fixed length instructions, in a manner compatible with existing code

ADAPTIVE THREAD ID CACHE MECHANISM FOR AUTONOMIC PERFORMANCE TUNING

Local and global branch prediction information storage

Double-Width Instruction Queue for Instruction Execution

Early Conditional Branch Resolution

Hybrid Branch Prediction Scheme

Dual Path Issue for Conditional Branch Instructions

Predicated issue for conditional branch instructions

Simple load and store disambiguation and scheduling at predecode

A Fast and Inexpensive Store-Load Conflict Scheduling and Forwarding Mechanism

Efficient handling of mostly read data in a computer server

Scheduling instructions in a cascaded delayed execution pipeline to minimize pipeline stalls caused by a cache miss

D-cache miss prediction and scheduling

Self prefetching L2 cache mechanism for instruction lines

Multiple parallel pipeline processor having self-repairing capability

Floating point unit power reduction via inhibiting register file write during tight loop execution

Multiply-sum dot product instruction with mask and splat

Method and system for reducing power consumption in a computing device when the computing device executes instructions in a tight loop

Effectively infinite branch prediction table mechanism

Fixed point unit power reduction mechanism for superscalar loop execution

Completion table configured to track a larger number of outstanding instructions without increasing the size of the completion table

Power reduction mechanism for floating point register file reads

System for allowing only a partial value prediction field/cache size

Floating point unit power reduction scheme

Icache-based value prediction mechanism

Extending the number of instruction bits in processors with fixed length instructions, in a manner compatible with existing code

Pipeline recirculation for data misprediction in a fast-load data cache

Methods and arrangements for repairing ports

Processor power and energy management

Automatic temporary precision reduction for enhanced compression

Adaptive memory compression

Reduction of cache miss rates using shared private caches

Adaptive thread ID cache mechanism for autonomic performance tuning

Runtime repairable processor

Dual array read port functionality from a one port SRAM