Inventor profile of:

Angelo Pinto

City:

Allen, Texas

Country:

United States

Published Applications:

15

Last publication date:

2012-06-28

Top Assignees for applications by Angelo Pinto

The entities that hold a legal rights for patent applications filed by inventor Pinto Angelo:

Recent patent applications by Pinto Angelo

Angelo Pinto from Allen, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2012-06-28
US20120164802A1
Electricity

Advanced CMOS using super steep retrograde wells

#2 | 2011-05-12
US20110111553A1
Electricity

Advanced CMOS using super steep retrograde wells

#3 | 2010-02-25
US20100047993A1
Electricity

Integration of high-k metal gate stack into direct silicon bonding (DSB) hybrid orientation technology (HOT) pMOS process flow

#4 | 2009-05-21
US20090130817A1
Electricity

Method to eliminate re-crystallization border defects generated during solid phase epitaxy of a DSB substrate

#5 | 2009-01-15
US20090014805A1
Electricity

Method to improve performance of secondary active components in an esige CMOS technology

#6 | 2008-12-18
US20080308847A1
Electricity

Method of making (100) NMOS and (110) PMOS sidewall surface on the same fin orientation for multiple gate MOSFET with DSB substrate

#7 | 2008-06-05
US20080132012A1
Electricity

Advanced CMOS using super steep retrograde wells

#8 | 2008-06-05
US20080128821A1
Electricity

Semiconductor Device Manufactured Using Passivation of Crystal Domain Interfaces in Hybrid Orientation Technology

#9 | 2006-09-07
US20060197158A1
Electricity

Advanced CMOS using super steep retrograde wells

#10 | 2005-11-10
US20050250289A1
Electricity

Control of dopant diffusion from buried layers in bipolar integrated circuits

#11 | 2005-08-09
US10818931
-

Lateral heterojunction bipolar transistor

#12 | 2005-05-17
US9967187
-

Bipolar junction transistor with a counterdoped collector region

#13 | 2005-05-12
US20050098093A1
Chemistry; metallurgy

Method of fabricating an epitaxial silicon-germanium layer and an integrated semiconductor device comprising an epitaxial arsenic in-situ doped silicon-germanium layer

#14 | 2005-05-03
US10007954
-

Method for manufacturing a bipolar junction transistor

#15 | 2005-02-17
US20050037588A1
Electricity

Structure of semiconductor device with sinker contact region

InventorID:

3203430 ⎘