Dallas, Texas
United States
46
2012-06-28
The entities that hold a legal rights for patent applications filed by inventor Howard Gregory E.:
Gregory E. Howard from Dallas, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Advanced CMOS using super steep retrograde wells
#2 | 2011-05-12Advanced CMOS using super steep retrograde wells
#3 | 2010-11-04Control of dopant diffusion from buried layers in bipolar integrated circuits
#4 | 2009-12-10Array-processed stacked semiconductor packages
#5 | 2009-10-29Heat extraction from packaged semiconductor chips, scalable with chip area
#6 | 2009-05-21Advanced CMOS using super steep retrograde wells
#7 | 2009-03-05SEMICONDUCTOR PACKAGE HAVING A GRID ARRAY OF PIN-ATTACHED BALLS
#8 | 2009-01-29Heat extraction from packaged semiconductor chips, scalable with chip area
#9 | 2009-01-01THERMALLY ENHANCED SEMICONDUCTOR DEVICES
#10 | 2008-06-05Advanced CMOS using super steep retrograde wells
#11 | 2008-01-31Array-Processed Stacked Semiconductor Packages
#12 | 2007-12-06Versatile system for cross-lateral junction field effect transistor
#13 | 2007-12-06Versatile system for cross-lateral junction field effect transistor
#14 | 2007-10-25Transistor apparatus
#15 | 2006-11-30MOSFET having channel in bulk semiconductor and source/drain on insulator, and method of fabrication
#16 | 2006-09-07Advanced CMOS using super steep retrograde wells
#17 | 2006-08-10Advanced CMOS using super steep retrograde wells
#18 | 2006-07-13Versatile system for cross-lateral junction field effect transistor
#19 | 2006-06-20Advanced CMOS using super steep retrograde wells
#20 | 2006-04-25Carbide emitter mask etch stop
#21 | 2006-03-02System and method for modeling an integrated circuit system
#22 | 2006-02-02Semiconductor package having a grid array of pin-attached balls
#23 | 2006-01-19Bipolar transistor having base over buried insulating and polycrystalline regions
#24 | 2005-12-15MOSFET having channel in bulk semiconductor and source/drain on insulator, and method of fabrication
#25 | 2005-11-24On chip heating for electrical trimming of polysilicon and polysilicon-silicon-germanium resistors and electrically programmable fuses for integrated circuits
#26 | 2005-11-10Control of dopant diffusion from buried layers in bipolar integrated circuits
#27 | 2005-11-10Implant-controlled-channel vertical JFET
#28 | 2005-10-25On chip heating for electrical trimming of polysilicon and polysilicon-silicon-germanium resistors and electrically programmable fuses for integrated circuits
#29 | 2005-09-08Double diffused vertical JFET
#30 | 2005-09-01Via structure of packages for high frequency semiconductor devices
#31 | 2005-08-09Lateral heterojunction bipolar transistor
#32 | 2005-06-30Scribe street width reduction by deep trench and shallow saw cut
#33 | 2005-06-23Flexible package with rigid substrate segments for high density integrated circuit systems
#34 | 2005-06-23Wire loop grid array package
#35 | 2005-06-23System and method for delivering power to a semiconductor device
#36 | 2005-06-16Semiconductor packages for enhanced number of terminals, speed and power performance
#37 | 2005-06-14Method for constructing a metal oxide semiconductor field effect transistor
#38 | 2005-05-17Bipolar junction transistor with a counterdoped collector region
#39 | 2005-05-10Scribe street width reduction by deep trench and shallow saw cut
#40 | 2005-05-03Method for manufacturing a bipolar junction transistor
#41 | 2005-03-24Method of forming integrated circuit contacts
#42 | 2005-01-25Semiconductor circuit with mechanically attached lid
#43 | 2005-01-20Double diffused vertical JFET
#44 | 2005-01-13Semiconductor packages for enhanced number of terminals, speed and power performance
#45 | 2005-01-13Implant-controlled-channel vertical JFET
#46 | 2005-01-04Integrated process for high voltage and high performance silicon-on-insulator bipolar devices
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