Inventor profile of:

Gregory E. Howard

City:

Dallas, Texas

Country:

United States

Published Applications:

46

Last publication date:

2012-06-28

Top Assignees for applications by Gregory E. Howard

The entities that hold a legal rights for patent applications filed by inventor Howard Gregory E.:

Recent patent applications by Howard Gregory E.

Gregory E. Howard from Dallas, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2012-06-28
US20120164802A1
Electricity

Advanced CMOS using super steep retrograde wells

#2 | 2011-05-12
US20110111553A1
Electricity

Advanced CMOS using super steep retrograde wells

#3 | 2010-11-04
US20100279481A1
Electricity

Control of dopant diffusion from buried layers in bipolar integrated circuits

#4 | 2009-12-10
US20090305464A1
Electricity

Array-processed stacked semiconductor packages

#5 | 2009-10-29
US20090267218A1
Electricity

Heat extraction from packaged semiconductor chips, scalable with chip area

#6 | 2009-05-21
US20090130805A1
Electricity

Advanced CMOS using super steep retrograde wells

#7 | 2009-03-05
US20090061566A1
Electricity

SEMICONDUCTOR PACKAGE HAVING A GRID ARRAY OF PIN-ATTACHED BALLS

#8 | 2009-01-29
US20090026605A1
Electricity

Heat extraction from packaged semiconductor chips, scalable with chip area

#9 | 2009-01-01
US20090001517A1
Electricity

THERMALLY ENHANCED SEMICONDUCTOR DEVICES

#10 | 2008-06-05
US20080132012A1
Electricity

Advanced CMOS using super steep retrograde wells

#11 | 2008-01-31
US20080023805A1
Electricity

Array-Processed Stacked Semiconductor Packages

#12 | 2007-12-06
US20070281408A1
Electricity

Versatile system for cross-lateral junction field effect transistor

#13 | 2007-12-06
US20070281407A1
Electricity

Versatile system for cross-lateral junction field effect transistor

#14 | 2007-10-25
US20070246800A1
Electricity

Transistor apparatus

#15 | 2006-11-30
US20060267061A1
Electricity

MOSFET having channel in bulk semiconductor and source/drain on insulator, and method of fabrication

#16 | 2006-09-07
US20060197158A1
Electricity

Advanced CMOS using super steep retrograde wells

#17 | 2006-08-10
US20060175657A1
Electricity

Advanced CMOS using super steep retrograde wells

#18 | 2006-07-13
US20060151804A1
Electricity

Versatile system for cross-lateral junction field effect transistor

#19 | 2006-06-20
US9948856
-

Advanced CMOS using super steep retrograde wells

#20 | 2006-04-25
US10657530
-

Carbide emitter mask etch stop

#21 | 2006-03-02
US20060048081A1
Physics

System and method for modeling an integrated circuit system

#22 | 2006-02-02
US20060021795A1
Electricity

Semiconductor package having a grid array of pin-attached balls

#23 | 2006-01-19
US20060011943A1
Physics

Bipolar transistor having base over buried insulating and polycrystalline regions

#24 | 2005-12-15
US20050274951A1
Electricity

MOSFET having channel in bulk semiconductor and source/drain on insulator, and method of fabrication

#25 | 2005-11-24
US20050258990A1
Electricity

On chip heating for electrical trimming of polysilicon and polysilicon-silicon-germanium resistors and electrically programmable fuses for integrated circuits

#26 | 2005-11-10
US20050250289A1
Electricity

Control of dopant diffusion from buried layers in bipolar integrated circuits

#27 | 2005-11-10
US20050247955A1
Electricity

Implant-controlled-channel vertical JFET

#28 | 2005-10-25
US9949541
-

On chip heating for electrical trimming of polysilicon and polysilicon-silicon-germanium resistors and electrically programmable fuses for integrated circuits

#29 | 2005-09-08
US20050194621A1
Electricity

Double diffused vertical JFET

#30 | 2005-09-01
US20050191785A1
Electricity

Via structure of packages for high frequency semiconductor devices

#31 | 2005-08-09
US10818931
-

Lateral heterojunction bipolar transistor

#32 | 2005-06-30
US20050140030A1
Electricity

Scribe street width reduction by deep trench and shallow saw cut

#33 | 2005-06-23
US20050133929A1
Electricity

Flexible package with rigid substrate segments for high density integrated circuit systems

#34 | 2005-06-23
US20050133928A1
Electricity

Wire loop grid array package

#35 | 2005-06-23
US20050133901A1
Electricity

System and method for delivering power to a semiconductor device

#36 | 2005-06-16
US20050127492A1
Electricity

Semiconductor packages for enhanced number of terminals, speed and power performance

#37 | 2005-06-14
US10719198
-

Method for constructing a metal oxide semiconductor field effect transistor

#38 | 2005-05-17
US9967187
-

Bipolar junction transistor with a counterdoped collector region

#39 | 2005-05-10
US10445163
-

Scribe street width reduction by deep trench and shallow saw cut

#40 | 2005-05-03
US10007954
-

Method for manufacturing a bipolar junction transistor

#41 | 2005-03-24
US20050064692A1
Electricity

Method of forming integrated circuit contacts

#42 | 2005-01-25
US10676669
-

Semiconductor circuit with mechanically attached lid

#43 | 2005-01-20
US20050012111A1
Electricity

Double diffused vertical JFET

#44 | 2005-01-13
US20050006739A1
Electricity

Semiconductor packages for enhanced number of terminals, speed and power performance

#45 | 2005-01-13
US20050006663A1
Electricity

Implant-controlled-channel vertical JFET

#46 | 2005-01-04
US10844144
-

Integrated process for high voltage and high performance silicon-on-insulator bipolar devices

InventorID:

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