Michael D. Snyder

Hardware Verification of Dynamically Generated Code

Processor Instruction for Secure Pointer Arithmetic

Translation Lookaside Buffer Entry Locking

Hardware verification of dynamically generated code

Hardware verification of dynamically generated code

Virtual channel support using write table

Methods for testing a memory embedded in an integrated circuit

Indicating disabled thread to other threads when contending instructions complete execution to ensure safe shared resource condition

Processor with hardware thread control logic indicating disable status when instructions accessing shared resources are completed for safe shared resource condition

Error detection in a content addressable memory (CAM)

Technique for determining if a logical sum of a first operand and a second operand is the same as a third operand

Integrated circuit having an embedded memory and method for testing the memory

Voltage-based memory size scaling in a data processing system

Permissions checking for data processing instructions

Data processor for processing a decorated storage notify

Interrupt controller for accelerated interrupt handling in a data processing system and method thereof

DEBUG INSTRUCTION FOR USE IN A MULTI-THREADED DATA PROCESSING SYSTEM

Debug instruction for execution by a first thread to generate a debug event in a second thread to cause a halting operation

Memory operation testing

Qualification of conditional debug instructions based on address

Completion continue on thread switch based on instruction progress metric mechanism for a microprocessor

System and method for processing potentially self-inconsistent memory transactions

Polling using reservation mechanism

PSEUDO LEAST RECENTLY USED (PLRU) CACHE REPLACEMENT

Integrated circuit memory having dynamically adjustable read margin and method therefor

Forward progress mechanism for a multithreaded processor

Debug instruction for use in a data processing system