Shom Ponoth

Pad bonding employing a self-aligned plated liner for adhesion enhancement

METHOD TO GENERATE AIRGAPS WITH A TEMPLATE FIRST SCHEME AND A SELF ALIGNED BLOCKOUT MASK AND STRUCTURE

Grain growth promotion layer for semiconductor interconnect structures

METHOD FOR ENABLING HARD MASK FREE INTEGRATION OF ULTRA LOW-K MATERIALS AND STRUCTURES PRODUCED THEREBY

Plating seed layer including an oxygen/nitrogen transition region for barrier enhancement

Conductor-dielectric structure and method for fabricating

Method for fabricating back end of the line structures with liner and seed materials

DENSIFYING SURFACE OF POROUS DIELECTRIC LAYER USING GAS CLUSTER ION BEAM

AIR-GAP INTERCONNECT STRUCTURES WITH SELECTIVE CAP

METHOD FOR ENABLING HARD MASK FREE INTEGRATION OF ULTRA LOW-K MATERIALS AND STRUCTURES PRODUCED THEREBY

Back end of the line structures with liner and noble metal layer

Grain growth promotion layer for semiconductor interconnect structures

Method of making a semiconductor structure with a plating enhancement layer

INTEGRATED LITHOGRAPHY AND ETCH FOR DUAL DAMASCENE STRUCTURES

Plating seed layer including an oxygen/nitrogen transition region for barrier enhancement

Conductor-dielectric structure and method for fabricating

Plating seed layer including an oxygen/nitrogen transition region for barrier enhancement

METHOD FOR PROTECTING A SEMICONDUCTOR DEVICE FROM CARBON DEPLETION BASED DAMAGE

Method to create air gaps using non-plasma processes to damage ILD materials

Method to create region specific exposure in a layer

Maintaining uniform CMP hard mask thickness