Peter J. Klim

TEST STRUCTURE AND METHODOLOGY FOR THREE-DIMENSIONAL SEMICONDUCTOR STRUCTURES

Test structure and methodology for three-dimensional semiconductor structures

Techniques for reducing power requirements of an integrated circuit

Test structure and methodology for three-dimensional semiconductor structures

Structure for a Limited Switch Dynamic Logic Cell Based Register

Limited switch dynamic logic cell based register

Structure for reduced area active above-ground and below-supply noise suppression circuits

Reduced area active above-ground and below-supply noise suppression circuits

Structure for Transmission Gate Multiplexer

Transmission gate multiplexer

Dynamically shared group completion table between multiple threads

Transmission gate multiplexer

Structure for a configurable low power high fan-in multiplexer

Method and apparatus for a configurable low power high fan-in multiplexer

High performance, low power, dynamically latched up/down counter

Self-Resetting Phase Frequency Detector with Multiple Ranges of Clock Difference

Structure for automated transistor tuning in an integrated circuit design

System and method of selective row energization based on write data

Double-edge triggered scannable pulsed flip-flop for high frequency and/or low power applications

Limited switch dynamic logic cell based register

Virtual power rails for integrated circuits

DOUBLE-EDGE TRIGGERED SCANNABLE PULSED FLIP-FLOP FOR HIGH FREQUENCY AND/OR LOW POWER APPLICATIONS

Method, System and Program Product for Automated Transistor Tuning in an Integrated Circuit Design

Memory device with control circuit for regulating power supply voltage

High-speed low-power integrated circuit interconnects

Memory Device with Control Circuit for Regulating Power Supply Voltage

SCANNABLE DOMINO LATCH REDUNDANCY FOR SOFT ERROR RATE PROTECTION WITH COLLISION AVOIDANCE

System and method of selective row energization based on write data

Memory device with control circuit for regulating power supply voltage