Kenneth Alan Dockser

WRITE-ALLOCATION FOR A CACHE BASED ON EXECUTE PERMISSIONS

Method and apparatus for cache tag compression

Division and root computation with fast result formatting

HIGH PERFORMANCE DIVISION AND ROOT COMPUTATION UNIT

Method and apparatus for selective renaming in a microprocessor

Optimizing performance for context-dependent instructions

FLOATING-POINT ADDER WITH OPERAND SHIFTING BASED ON A PREDICTED EXPONENT DIFFERENCE

Processor with Hazard Tracking Employing Register Range Compares

Processor with a Hybrid Instruction Queue with Instruction Elaboration Between Sections

Processor with a coprocessor having early access to not-yet issued instructions

Hybrid queue for storing instructions from fetch queue directly in out-of-order queue or temporarily in in-order queue until space is available

Software selectable adjustment of SIMD parallelism

Methods and Apparatus for a Read, Merge and Write Register File

Mode-based multiply-add recoding for denormal operands

Software selectable adjustment of SIMD parallelism

Latency insensitive FIFO signaling protocol

Method and apparatus for executing processor instructions based on a dynamically alterable delay

Mode-based multiply-add recoding for denormal operands

Controlled-precision iterative arithmetic logic unit

Floating-point processor with reduced power requirements for selectable subprecision

Pre-saturating fixed-point multiplier

Floating-point processor with selectable subprecision

Microprocessor with automatic selection of processing parallelism mode based on width data of instructions

Software selectable adjustment of SIMD parallelism

Method and system for reducing power consumption of a programmable processor

Latency insensitive FIFO signaling protocol

System and method wherein conditional instructions unconditionally provide output