Plano, Texas
United States
54
2026-05-21
The entities that hold a legal rights for patent applications filed by inventor Rahman Mujibur:
Mujibur Rahman from Plano, US has applied for patents for these inventions. The list has both pending applications and granted patents:
SORTING VECTOR ELEMENTS USING A MAPPING OF ELEMENTS
#2 | 2026-02-12METHOD AND APPARATUS FOR IMPLIED BIT HANDLING IN FLOATING POINT MULTIPLICATION
#3 | 2026-01-29Permutation for Vector Operations
#4 | 2026-01-15Multiple Multiplication Units in a Data Path
#5 | 2026-01-08Method and Apparatus for Vector Sorting using Vector Permutation Logic
#6 | 2025-04-24VECTOR TRANSFORMATION IN PARALLEL WITH ARITHMETIC OPERATION
#7 | 2024-12-19METHOD AND APPARATUS FOR VECTOR PERMUTATION
#8 | 2024-11-14METHOD AND APPARATUS FOR PERMUTING STREAMED DATA ELEMENTS
#9 | 2024-10-24SORTING VECTOR ELEMENTS USING A COUNT VALUE
#10 | 2024-10-24Vector Based Matrix Multiplication
#11 | 2024-10-03METHOD AND APPARATUS FOR IMPLIED BIT HANDLING IN FLOATING POINT MULTIPLICATION
#12 | 2024-09-19Method and Apparatus for Dual Issue Multiply Instructions
#13 | 2024-06-27Multiple Multiplication Units in a Data Path
#14 | 2024-06-27VECTOR SIMD VLIW DATA PATH ARCHITECTURE
#15 | 2024-02-08Method and Apparatus for Vector Sorting using Vector Permutation Logic
#16 | 2024-01-04Processing device with vector transformation execution
#17 | 2023-11-02Method and apparatus for dual issue multiply instructions
#18 | 2023-10-19Method and Apparatus for Vector Based Finite Impulse Response (FIR) Filtering
#19 | 2023-09-14Method and apparatus for permuting streamed data elements
#20 | 2023-07-20METHOD AND APPARATUS TO SORT A VECTOR FOR A BITONIC SORTING ALGORITHM
#21 | 2023-06-01Vector SIMD VLIW data path architecture
#22 | 2023-03-30Method and apparatus for vector sorting
#23 | 2023-03-16Method and apparatus for implied bit handling in floating point multiplication
#24 | 2023-02-09Method and apparatus for vector sorting using vector permutation logic
#25 | 2022-09-08Method and apparatus for vector based matrix multiplication
#26 | 2022-08-18Processing device with vector transformation execution
#27 | 2022-07-21Method and apparatus for dual issue multiply instructions
#28 | 2022-06-30Method and apparatus for dual multiplication units in a data path
#29 | 2022-05-19Method and apparatus to sort a vector for a bitonic sorting algorithm
#30 | 2022-05-19Method and apparatus for permuting streamed data elements
#31 | 2021-11-18Method and apparatus for vector sorting
#32 | 2021-11-11Method and apparatus for vector permutation
#33 | 2020-11-26Method and apparatus for vector based finite impulse response (FIR) filtering
#34 | 2020-11-26Method and apparatus to sort a vector for a bitonic sorting algorithm
#35 | 2020-11-26Method and apparatus for vector sorting using vector permutation logic
#36 | 2020-11-26Processing device with vector transformation execution
#37 | 2020-11-26Method and apparatus for permuting streamed data elements
#38 | 2020-11-26Method and apparatus for vector based matrix multiplication
#39 | 2020-11-26Method and apparatus for dual multiplication units in a data path
#40 | 2020-11-26Method and apparatus for vector sorting
#41 | 2020-11-26Method and apparatus for dual issue multiply instructions
#42 | 2020-11-26Method and apparatus for implied bit handling in floating point multiplication
#43 | 2020-10-08Vector SIMD VLIW data path architecture
#44 | 2019-12-12Method and apparatus for vector permutation
#45 | 2017-05-25Faster and more efficient different precision sum of absolute differences for dynamically configurable block searches for motion estimation
#46 | 2015-06-04Vector SIMD VLIW data path architecture
#47 | 2015-03-19Faster and more efficient different precision sum of absolute differences for dynamically configurable block searches for motion estimation
#48 | 2015-01-15Highly efficient different precision complex multiply accumulate to enhance chip rate functionality in DSSS cellular systems
#49 | 2014-06-26Three-term predictive adder and/or subtracter
#50 | 2013-07-04Family of multiplexer/flip-flops with enhanced testability
#51 | 2013-01-10Three-term predictive adder and/or subtracter
#52 | 2012-07-26Circuit which performs split precision, signed/unsigned, fixed and floating point, real and complex multiplication
#53 | 2012-03-29Dual register data path architecture with registers in a data file divided into groups and sub-groups
#54 | 2012-02-09Test chain testability in a system for testing tri-state functionality
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