Inventor profile of:

Kai Chirca

City:

Richardson, Texas

Country:

United States

Published Applications:

18

Last publication date:

2023-12-28

Top Assignees for applications by Kai Chirca

The entities that hold a legal rights for patent applications filed by inventor Chirca Kai:

Recent patent applications by Chirca Kai

Kai Chirca from Richardson, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2023-12-28
US20230418759A1
Physics

Slot/sub-slot prefetch architecture for multiple memory requestors

#2 | 2021-11-11
US20210349827A1
Physics

Slot/sub-slot prefetch architecture for multiple memory requestors

#3 | 2020-02-20
US20200057723A1
Physics

Slot/sub-slot prefetch architecture for multiple memory requestors

#4 | 2018-08-23
US20180239710A1
Physics

Slot/sub-slot prefetch architecture for multiple memory requestors

#5 | 2014-06-26
US20140181165A1
Physics

Three-term predictive adder and/or subtracter

#6 | 2013-01-10
US20130013656A1
Physics

Three-term predictive adder and/or subtracter

#7 | 2012-12-13
US20120317322A1
Physics

High fairness variable priority arbitration method

#8 | 2012-03-29
US20120079202A1
Physics

Multistream prefetch buffer

#9 | 2012-03-22
US20120072796A1
Physics

Memory controller with automatic error detection and correction

#10 | 2012-03-22
US20120072702A1
Physics

Prefetcher with arbitrary downstream prefetch cancelation

#11 | 2012-03-22
US20120072673A1
Physics

Speculation-aware memory controller arbiter

#12 | 2012-03-22
US20120072671A1
Physics

Prefetch stream filter with FIFO allocation and stream direction prediction

#13 | 2012-03-22
US20120072668A1
Physics

Slot/sub-slot prefetch architecture for multiple memory requestors

#14 | 2012-03-22
US20120072667A1
Physics

Variable line size prefetcher for multiple memory requestors

#15 | 2012-03-22
US20120072631A1
Physics

Multilayer arbitration for access to multiple destinations

#16 | 2012-02-02
US20120030431A1
Physics

Predictive sequential prefetching for data caching

#17 | 2010-08-05
US20100199064A1
Physics

Fast address translation for linear and circular modes

#18 | 2005-09-15
US20050203983A1
Physics

Arithmetic circuit with balanced logic levels for low-power operation

InventorID:

32852 ⎘