Boise, Idaho
United States
45
2012-11-08
The entities that hold a legal rights for patent applications filed by inventor Johnson Brian:
Brian Johnson from Boise, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Data storage system, electronic system, and telecommunications system
#2 | 2011-06-30Data storage system, electronic system, and telecommunications system
#3 | 2011-02-17Memory device and method having low-power, high write latency mode and high-power, low write latency mode and/or independently selectable write latency
#4 | 2010-08-05Method and apparatus for address FIFO for high bandwidth command/address busses in digital storage system
#5 | 2009-03-12Memory device and method having low-power, high write latency mode and high-power, low write latency mode and/or independently selectable write latency
#6 | 2008-04-17Memory device and method having data path with multiple prefetch I/O configurations
#7 | 2007-11-22Memory device and method having low-power, high write latency mode and high-power, low write latency mode and/or independently selectable write latency
#8 | 2007-05-24Apparatus and method for mounting microelectronic devices on a mirrored board assembly
#9 | 2007-03-15Memory device and method having data path with multiple prefetch I/O configurations
#10 | 2007-01-25Method and apparatus for calibrating driver impedance
#11 | 2007-01-09Method and structures for reduced parasitic capacitance in integrated circuit metallizations
#12 | 2007-01-02Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same
#13 | 2006-11-23Method and apparatus for address FIFO for high-bandwidth command/address busses in digital storage system
#14 | 2006-10-31Method and apparatus for calibrating driver impedance
#15 | 2006-09-14Method and system for generating reference voltages for signal receivers
#16 | 2006-08-01Method and apparatus for address FIFO for high-bandwidth command/address busses in digital storage system
#17 | 2006-07-13Multiphase clock generation
#18 | 2006-07-13Memory device and method having low-power, high write latency mode and high-power, low write latency mode and/or independently selectable write latency
#19 | 2006-06-29Memory system and method for strobing data, command and address signals
#20 | 2006-06-29Memory system and method for strobing data, command and address signals
#21 | 2006-06-22Memory system and method for strobing data, command and address signals
#22 | 2006-06-15Memory system and method for strobing data, command and address signals
#23 | 2006-06-06Apparatus and method for clock domain crossing with integrated decode
#24 | 2006-04-20Memory device and method having data path with multiple prefetch I/O configurations
#25 | 2006-03-14Simulated circuit node initializing and monitoring
#26 | 2006-03-02Method and system for generating reference voltages for signal receivers
#27 | 2006-03-02Memory system and method for strobing data, command and address signals
#28 | 2005-09-29Multiphase clock generators
#29 | 2005-08-25Timing calibration pattern for SLDRAM
#30 | 2005-08-23Memory device and method having low-power, high write latency mode and high-power, low write latency mode and/or independently selectable write latency
#31 | 2005-08-16Method and apparatus for establishing and maintaining desired read latency in high-speed DRAM
#32 | 2005-06-21Method and structures for reduced parasitic capacitance in integrated circuit metallizations
#33 | 2005-06-09Memory device and method having data path with multiple prefetch I/O configurations
#34 | 2005-06-09Memory device and method having low-power, high write latency mode and high-power, low write latency mode and/or independently selectable write latency
#35 | 2005-06-09Memory device and method having data path with multiple prefetch I/O configurations
#36 | 2005-06-02Memory device and method having low-power, high write latency mode and high-power, low write latency mode and/or independently selectable write latency
#37 | 2005-05-05Multi-mode synchronous memory device and methods of operating and testing same
#38 | 2005-05-03Timing calibration pattern for SLDRAM
#39 | 2005-04-19Memory device and method having data path with multiple prefetch I/O configurations
#40 | 2005-04-05Apparatus and method for mounting microelectronic devices on a mirrored board assembly
#41 | 2005-03-10Multiphase clock generators
#42 | 2005-02-01System latency levelization for read data
#43 | 2005-01-13Apparatus and method for mounting microelectronic devices on a mirrored board assembly
#44 | 2005-01-13Apparatus and method for mounting microelectronic devices on a mirrored board assembly
#45 | 2005-01-11Multi-mode synchronous memory device and methods of operating and testing same
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