Jericho Center, Vermont
United States
23
2026-06-18
The entities that hold a legal rights for patent applications filed by inventor Hook Terence B.:
Terence B. Hook from Jericho Center, US has applied for patents for these inventions. The list has both pending applications and granted patents:
LATERAL IDEAL DIODE FOR BANDGAP REFERENCE IN NANOSHEET TECHNOLOGY
#2 | 2026-06-18CHARGING DAMAGE PROTECTION FOR BACKSIDE POWER DELIVERY
#3 | 2025-09-04CELLS WITH INTEGRATED PROTECTION DIODES
#4 | 2025-06-19STRUCTURES FOR STACKED-FET ANALOG APPLICATIONS
#5 | 2025-06-19SEMICONDUCTOR DEVICE WITH LATERAL DIODES AND STACKED FETS
#6 | 2025-06-19SUBSTRATE-LESS PASSIVE DEVICE SOLUTION FOR BACKSIDE POWER DISTRIBUTION NETWORK
#7 | 2025-05-15MULTI-FET VERTICAL STACK MODELING
#8 | 2025-05-01BONDING A WAFER WITH A SUBSTRATE TO A WAFER WITH BACKSIDE INTERCONNECT WIRING
#9 | 2025-03-06ANTENNA DIODE INTEGRATION WITH BACKSIDE BACK END OF THE LINE NETWORK
#10 | 2025-01-23EXTENDED BACKSIDE CONTACT IN STACK NANOSHEET
#11 | 2018-07-26Prevention of charging damage in full-depletion devices
#12 | 2017-11-16Prevention of charging damage in full-depletion devices
#13 | 2017-11-16Prevention of charging damage in full-depletion devices
#14 | 2016-12-13Field effect transistor having delay element with back gate
#15 | 2015-04-14Estimating transistor characteristics and tolerances for compact modeling
#16 | 2015-03-05Integrated circuit including DRAM and SRAM/logic
#17 | 2013-07-11Integrated circuit including DRAM and SRAM/logic
#18 | 2013-07-11Integrated circuit including DRAM and SRAM/logic
#19 | 2013-07-11Integrated circuit including DRAM and SRAM/logic
#20 | 2008-01-24Precision passive circuit structure
#21 | 2007-03-01CMOS well structure and method of forming the same
#22 | 2005-10-20Structure and method for providing precision passive elements
#23 | 2005-05-19CMOS well structure and method of forming the same
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