Jericho, Vermont
United States
31
2018-07-19
The entities that hold a legal rights for patent applications filed by inventor Feilchenfeld Natalie B.:
Natalie B. Feilchenfeld from Jericho, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Lateral PiN diodes and schottky diodes
#2 | 2018-02-13Structures with contact trenches and isolation trenches
#3 | 2017-10-24Semiconductor structure with a dopant implant region having a linearly graded conductivity level and method of forming the structure
#4 | 2017-09-19Semiconductor structure with a dopant implant region having a linearly graded conductivity level and method of forming the structure
#5 | 2016-12-22Device structures for a silicon-on-insulator substrate with a high-resistance handle wafer
#6 | 2016-06-30Tapered gate oxide in LDMOS devices
#7 | 2016-06-30Semiconductor structures with isolated ohmic trenches and stand-alone isolation trenches and related method
#8 | 2016-03-03Lateral PiN diodes and schottky diodes
#9 | 2016-02-11SELF-ALIGNED BIPOLAR JUNCTION TRANSISTOR HAVING SELF-PLANARIZING ISOLATION RAISED BASE STRUCTURES
#10 | 2015-12-03Semiconductor structures with isolated ohmic trenches and stand-alone isolation trenches and related method
#11 | 2015-09-10Dual shallow trench isolation (STI) structure for field effect transistor (FET)
#12 | 2014-11-27High voltage laterally diffused metal oxide semiconductor
#13 | 2014-11-13Self-aligned bipolar junction transistor having self-planarizing isolation raised base structures
#14 | 2014-11-06DUAL SHALLOW TRENCH ISOLATION (STI) FIELD EFFECT TRANSISTOR (FET) AND METHODS OF FORMING
#15 | 2014-08-28Interdigitated capacitors with a zero quadratic voltage coefficient of capacitance or zero linear temperature coefficient of capacitance
#16 | 2013-11-14Isolated zener diode, an integrated circuit incorporating multiple instances of the zener diode, a method of forming the zener diode and a design structure for the zener diode
#17 | 2013-07-11Isolated Zener diode
#18 | 2012-12-20Bipolar transistor with raised extrinsic self-aligned base using selective epitaxial growth for BiCMOS integration
#19 | 2012-05-24Lateral diffusion field effect transistor with drain region self-aligned to gate electrode
#20 | 2011-03-17Bipolar transistor with raised extrinsic self-aligned base using selective epitaxial growth for BiCMOS integration
#21 | 2010-06-17Method and structure for creation of a metal insulator metal capacitor
#22 | 2010-05-13Optimized device isolation
#23 | 2009-10-22Lateral diffusion field effect transistor with drain region self-aligned to gate electrode
#24 | 2009-07-30Modifying layout of IC based on function of interconnect and related circuit and design structure
#25 | 2009-06-04Lateral diffusion field effect transistor with a trench field plate
#26 | 2009-04-30Lateral diffusion field effect transistor with asymmetric gate dielectric profile
#27 | 2008-08-28Bipolar transistor with raised extrinsic self-aligned base using selective epitaxial growth for BiCMOS integration
#28 | 2008-01-24Formation of metal-insulator-metal capacitor simultaneously with aluminum metal wiring level using a hardmask
#29 | 2007-11-15Method and structure for creation of a metal insulator metal capacitor
#30 | 2005-12-08Formation of metal-insulator-metal capacitor simultaneously with aluminum metal wiring level using a hardmask
#31 | 2005-06-14Method to fabricate high-performance NPN transistors in a BiCMOS process
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