Inventor profile of:

Robert N. Leibowitz

City:

Boise, Idaho

Country:

United States

Published Applications:

21

Last publication date:

2016-01-07

Top Assignees for applications by Robert N. Leibowitz

The entities that hold a legal rights for patent applications filed by inventor Leibowitz Robert N.:

Recent patent applications by Leibowitz Robert N.

Robert N. Leibowitz from Boise, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2016-01-07
US20160004436A1
Physics

Host controller

#2 | 2015-06-04
US20150153956A1
Physics

Methods for controlling host memory access with memory devices and systems

#3 | 2014-09-18
US20140281811A1
Physics

Object oriented memory in solid state devices

#4 | 2014-07-03
US20140185620A1
Electricity

Packet deconstruction/reconstruction and link-control

#5 | 2014-04-17
US20140108678A1
Physics

Host controller

#6 | 2014-01-23
US20140025943A1
Physics

Booting in systems having devices coupled in a chained configuration

#7 | 2013-01-10
US20130013822A1
Physics

Host controller

#8 | 2012-11-15
US20120290826A1
Physics

Booting in systems having devices coupled in a chained configuration

#9 | 2012-11-08
US20120284466A1
Physics

Methods for controlling host memory access with memory devices and systems

#10 | 2012-11-08
US20120281537A1
Electricity

Packet deconstruction/reconstruction and link-control

#11 | 2012-08-16
US20120210025A1
Electricity

Device to device flow control within a chain of devices

#12 | 2012-08-02
US20120198201A1
Physics

Memory module with configurable input/output ports

#13 | 2011-03-03
US20110055436A1
Electricity

Device to device flow control within a chain of devices

#14 | 2011-02-24
US20110047366A1
Physics

Booting in systems having devices coupled in a chained configuration

#15 | 2011-02-10
US20110032823A1
Electricity

Packet deconstruction/reconstruction and link-control

#16 | 2010-12-09
US20100313065A1
Physics

Object oriented memory in solid state devices

#17 | 2010-12-09
US20100312973A1
Physics

Methods for controlling host memory access with memory devices and systems

#18 | 2010-07-29
US20100191874A1
Physics

Host controller

#19 | 2010-07-08
US20100174851A1
Physics

Memory system controller to manage wear leveling across a plurality of storage nodes

#20 | 2009-11-05
US20090276545A1
Physics

Memory module with configurable input/output ports

#21 | 2009-06-18
US20090157949A1
Physics

ADDRESS TRANSLATION BETWEEN A MEMORY CONTROLLER AND AN EXTERNAL MEMORY DEVICE

InventorID:

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