Haining Yang

Structure and method to enhance both NFET and PFET performance using different kinds of stressed layers

Gate conductor with a diffusion barrier

Structure for metal cap applications

Embedded interconnects, and methods for forming same

STRUCTURE AND METHOD OF FORMING TRANSITIONAL CONTACTS BETWEEN WIDE AND THIN BEOL WIRINGS

Enhanced interconnect structure

Structure and method for improved SRAM interconnect

Fully and uniformly silicided gate structure and method for forming same

FINFET STRUCTURE INCLUDING MULTIPLE SEMICONDUCTOR FIN CHANNEL HEIGHTS

Dual liner capping layer interconnect structure

Dual liner capping layer interconnect structure

Semiconductor Device Structures and Methods of Fabricating Semiconductor Device Structures for Use in SRAM Devices

STRUCTURE INCORPORATING SEMICONDUCTOR DEVICE STRUCTURES FOR USE IN SRAM DEVICES

Pattern enhancement by crystallographic etching

TRANSISTORS HAVING V-SHAPE SOURCE/DRAIN METAL CONTACTS

STRUCTURE FOR METAL CAP APPLICATIONS

STRUCTURE AND METHOD FOR FORMING ASYMMETRICAL OVERLAP CAPACITANCE IN FIELD EFFECT TRANSISTORS

Electronically programmable fuse having anode and link surrounded by low dielectric constant material

Method for fabricating shallow trench isolation structures using diblock copolymer patterning

Selective stress engineering for SRAM stability improvement

Gate conductor structure

Fully and uniformly silicided gate structure and method for forming same

HOT CARRIER DEGRADATION REDUCTION USING ION IMPLANTATION OF SILICON NITRIDE LAYER

Contact aperture and contact via with stepped sidewall and methods for fabrication thereof

Porous and dense hybrid interconnect structure and method of manufacture

Dual liner capping layer interconnect structure and method

STRUCTURE FOR CREATION OF A PROGRAMMABLE DEVICE

Structure and method for dual surface orientations for CMOS transistors

Device having enhanced stress state and related methods

Sub-lithographic gate length transistor using self-assembling polymers

METHOD AND STRUCTURE FOR REDUCING SOI DEVICE FLOATING BODY EFFECTS WITHOUT JUNCTION LEAKAGE

Sub-lithographic nano interconnect structures, and method for forming same

Enhanced interconnect structure

Structure and method for creation of a transistor

Sub-lithographic local interconnects, and methods for forming same

THREE-DIMENSIONAL SEMICONDUCTOR STRUCTURE AND METHOD FOR FABRICATION THEREOF

REDUCED-RESISTANCE FINFETS BY SIDEWALL SILICIDATION AND METHODS OF MANUFACTURING THE SAME

Device structures including backside contacts, and methods for forming same

Embedded interconnects, and methods for forming same

Structure and method to use low k stress liner to reduce parasitic capacitance

Strained MOSFETs on separated silicon layers

Structures incorporating semiconductor device structures with reduced junction capacitance and drain induced barrier lowering

Void formation for semiconductor junction capacitance reduction

Field effect transistors (FETs) with multiple and/or staircase silicide

CMOS DEVICES COMPRISING A CONTINUOUS STRESSOR LAYER WITH REGIONS OF OPPOSITE STRESSES, AND METHODS OF FABRICATING THE SAME

Sub-lithographic feature patterning using self-aligned self-assembly polymers

Transistors having v-shape source/drain metal contacts

Semiconductor device structures with reduced junction capacitance and drain induced barrier lowering and methods for fabricating such device structures and for fabricating a semiconductor-on-insulator substrate

PFETs and methods of manufacturing the same

Method for depositing a metal layer on a semiconductor interconnect structure having a capping layer

Reduced-resistance finFETs by sidewall silicidation and methods of manufacturing the same

Method of applying stresses to PFET and NFET transistor channels for improved performance

Reduction of boron diffusivity in pFETs

Structure and method for forming asymmetrical overlap capacitance in field effect transistors

Pattern enhancement by crystallographic etching

Method and structure for tungsten gate metal surface treatment while preventing oxidation

Field effect transistors (FETs) with multiple and/or staircase silicide

Method for forming self-aligned, dual silicon nitride liner for CMOS devices

IMPROVED MIM CAPACITOR STRUCTURE AND PROCESS

HOT CARRIER DEGRADATION REDUCTION USING ION IMPLANTATION OF SILICON NITRIDE LAYER

Device having enhanced stress state and related methods

Structure and method of applying stresses to PFET and NFET transistor channels for improved performance

METHOD AND STRUCTURE FOR IMPROVING CMOS DEVICE RELIABILITY USING COMBINATIONS OF INSULATING MATERIALS

Increasing carrier mobility in NFET and PFET transistors on a common wafer

Gate metal recess for oxidation protection and parasitic capacitance reduction

Increasing carrier mobility in NFET and PFET transistors on a common wafer

Structure and method to enhance both nFET and pFET performance using different kinds of stressed layers

Structure and method for eliminating metal contact to P-well of N-well shorts or high leakage paths using polysilicon liner