Mountain View, California
United States
45
2025-10-30
The entities that hold a legal rights for patent applications filed by inventor Hess Greg M.:
Greg M. Hess from Mountain View, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Memory Bit Cell for In-Memory Computation
#2 | 2025-05-22System Control Using Sparse Data
#3 | 2025-01-09System Control Using Sparse Data
#4 | 2024-04-04System control using sparse data
#5 | 2022-08-25System control using sparse data
#6 | 2022-03-31Memory Bit Cell for In-Memory Computation
#7 | 2021-08-12Efficient retention flop utilizing different voltage domain
#8 | 2020-12-10Power switch multiplexer with configurable overlap
#9 | 2020-10-08System control using sparse data
#10 | 2019-09-05Pulsed sub-VDD precharging of a bit line
#11 | 2019-03-28Low leakage power switch
#12 | 2019-03-28System control using sparse data
#13 | 2019-02-14Supply tracking delay element in multiple power domain designs
#14 | 2019-01-03Global bit line pre-charging and data latching in multi-banked memories using a delayed reset latch
#15 | 2016-12-27Power grid segmentation for memory arrays
#16 | 2016-08-18Shared gate fed sense amplifier
#17 | 2016-03-10Method and circuits for low latency initialization of static random access memory
#18 | 2016-03-03Selectable phase or cycle jitter detector
#19 | 2016-01-12Dynamic global memory bit line usage as storage node
#20 | 2015-12-03Configurable voltage reduction for register file
#21 | 2015-03-26Contention Prevention for Sequenced Power Up of Electronic Systems
#22 | 2014-06-26Zero keeper circuit with full design-for-test coverage
#23 | 2014-06-26Apparatus to suppress concurrent read and write word line access of the same memory element in a memory array
#24 | 2014-05-08Register file write ring oscillator
#25 | 2014-05-08Selectable phase or cycle jitter detector
#26 | 2014-05-08Sense amplifier soft-fail detection circuit
#27 | 2014-04-24Low Voltage Register File Cell Structure
#28 | 2013-12-19Dynamic level shifter circuit and ring oscillator using the same
#29 | 2013-06-20Multiplexer with level shifter
#30 | 2013-01-10Efficient handling of misaligned loads and stores
#31 | 2012-11-01Method and apparatus for power domain isolation during power down
#32 | 2012-10-11Leakage and NBTI reduction technique for memory
#33 | 2012-03-29Passgate for dynamic circuitry
#34 | 2012-02-23Level-Shifting Latch
#35 | 2011-10-20Leakage and NBTI reduction technique for memory
#36 | 2011-10-20Level shifter with embedded logic and low minimum voltage
#37 | 2011-09-29Low power memory array column redundancy mechanism
#38 | 2011-02-10Level shifter with embedded logic and low minimum voltage
#39 | 2010-12-30Leakage and NBTI reduction technique for memory
#40 | 2010-12-23Mechanism for measuring read current variability of SRAM cells
#41 | 2010-12-09Keeperless fully complementary static selection circuit
#42 | 2010-10-07Cache optimizations using multiple threshold voltage transistors
#43 | 2009-07-09Level shifter with embedded logic and low minimum voltage
#44 | 2007-07-05Digital jitter detector
#45 | 2007-05-17Digital leakage detector that detects transistor leakage current in an integrated circuit
33297 ⎘