Hung Q. Le

INSTRUCTION HANDLING FOR ACCUMULATION OF REGISTER RESULTS IN A MICROPROCESSOR

Instruction handling for accumulation of register results in a microprocessor

Check pointing of accumulator register results in a microprocessor

Thread-based organization of slice target register file entry in a microprocessor to permit writing scalar or vector data to portions of a single register file entry

Slice-target register file for microprocessor

Banked slice-target register file for wide dataflow execution in a microprocessor

Instruction handling for accumulation of register results in a microprocessor

Instruction streaming using copy select vector

Instruction streaming using state migration

Program instruction scheduling

Register file write using pointers

Saving and restoring a transaction memory state

Speculatively releasing store data before store instruction completion in a processor

Multiple streams execution for hard-to-predict branches in a microprocessor

Dual compare of least-significant-bit for dependency wake up from a fused instruction tag in a microprocessor

Independent mapping of threads

LOW POWER BACK-TO-BACK WAKE UP AND ISSUE FOR PAIRED ISSUE QUEUE IN A MICROPROCESSOR

Dispatching, allocating, and deallocating instructions with real/virtual and region tags in a queue in a processor

Dynamic update of the number of architected registers assigned to software threads using spill counts

Multiple Level History Buffer for Transaction Memory Support

Shared compare lanes for dependency wake up in a pair-based issue queue

Decoupling of conditional branches

Handling unaligned load operations in a multi-slice computer processor

Handling unaligned load operations in a multi-slice computer processor

Managing an issue queue for fused instructions and paired instructions in a microprocessor

Managing an issue queue for fused instructions and paired instructions in a microprocessor

Thread transition management

Managing an issue queue for fused instructions and paired instructions in a microprocessor

Managing an issue queue for fused instructions and paired instructions in a microprocessor

Converting multiple instructions into a single combined instruction with an extension opcode

Converting multiple instructions into a single combined instruction with an extension opcode

Speeding up younger store instruction execution after a sync instruction

Thread transition management

Multi-level history buffer for transaction memory in a microprocessor

Handling unaligned load operations in a multi-slice computer processor

Handling unaligned load operations in a multi-slice computer processor

Operation of a multi-slice processor with an expanded merge fetching queue

Operation of a multi-slice processor implementing a load/store unit maintaining rejected instructions

Operation of a multi-slice processor implementing a load/store unit maintaining rejected instructions

Dynamic update of the number of architected registers assigned to software threads using spill counts

Extended store forwarding for store misses without cache allocate

Independent mapping of threads

ADMINISTERING INSTRUCTION TAGS IN A COMPUTER PROCESSOR

Operation of a multi-slice processor implementing a load/store unit maintaining rejected instructions

Operation of a multi-slice processor implementing a load/store unit maintaining rejected instructions

Thread transition management

Operation of a multi-slice processor with an expanded merge fetching queue

TECHNIQUES FOR RESTORING PREVIOUS VALUES TO REGISTERS OF A PROCESSOR REGISTER FILE

Handling unaligned load operations in a multi-slice computer processor

Handling unaligned load operations in a multi-slice computer processor

Processing instructions in parallel with waw hazards and via a distributed history buffer in a microprocessor having a multi-execution slice architecture

Method and apparatus for execution of threads on processing slices using a history buffer for restoring architected register data via issued instructions

Method and apparatus for execution of threads on processing slices using a history buffer for recording architected register data

Transactional storage accesses supporting differing priority levels

Transactional storage accesses supporting differing priority levels

Split-level history buffer in a computer processing unit

Split-level history buffer in a computer processing unit

Split-level history buffer in a computer processing unit

Split-level history buffer in a computer processing unit

Universal history buffer to support multiple register types

Independent mapping of threads

Independent mapping of threads

Techniques for increasing vector processing utilization and efficiency through vector lane predication prediction

Thread transition management

Conditional transaction abort and precise abort handling

Detection of conflicts between transactions and page shootdowns

Recording and profiling transaction failure addresses of the abort-causing and approximate abort-causing data and instructions in hardware transactional memories

Recording and profiling transaction failure source addresses and states of validity indicator corresponding to addresses of aborted transaction in hardware transactional memories

Detection of conflicts between transactions and page shootdowns

Determining failure context in hardware transactional memories

Apparatus for determining failure context in hardware transactional memories

Instruction tracking system for processors

Speeding up younger store instruction execution after a sync instruction

Using Hardware Transaction Primitives for Implementing Non-Transactional Escape Actions Inside Transactions

HARDWARE ASSISTED SCHEDULING IN COMPUTER SYSTEM

Hardware assist thread for increasing code parallelism

Seamless interface for multi-threaded core accelerators

Thread transition management

Multi-level register file supporting multiple threads

Multi-level register file supporting multiple threads

Instruction tracking system for processors

Transactional memory system supporting unbroken suspended execution

Register file supporting transactional processing

Hardware assist thread for increasing code parallelism

System and method for implementing a hardware-supported thread assist under load lookahead mechanism for a microprocessor

System and method for implementing a software-supported thread assist mechanism for a microprocessor

Dynamically shared group completion table between multiple threads

Enhanced load lookahead prefetch in single threaded mode for a simultaneous multithreaded microprocessor

Enhanced single threaded execution in a simultaneous multithreaded microprocessor

Universal register rename mechanism for instructions with multiple targets in a microprocessor

Universal register rename mechanism for targets of different instruction types in a microprocessor

ADAPTIVE FETCH GATING IN MULTITHREADED PROCESSORS, FETCH CONTROL AND METHOD OF CONTROLLING FETCHES

Dynamic recalculation of resource vector at issue queue for steering of dependent instructions

ADAPTIVE FETCH GATING IN MULTITHREADED PROCESSORS, FETCH CONTROL AND METHOD OF CONTROLLING FETCHES

System for managing data dependency using bit field instruction destination vector identifying destination for execution results

SMT flush arbitration

Method of implementing precise, localized hardware-error workarounds under centralized control

Localized generation of global flush requests while guaranteeing forward progress of a processor

Method and apparatus for dynamic modification of microprocessor instruction group at dispatch

Dynamic recalculation of resource vector at issue queue for steering of dependent instructions