Danbury, Connecticut
United States
123
2019-08-01
The entities that hold a legal rights for patent applications filed by inventor Michael Maged M.:
Maged M. Michael from Danbury, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Interprocessor memory status communication
#2 | 2019-06-20Transactional lock elision with delayed lock checking
#3 | 2019-05-09Hint instruction for managing transactional aborts in transactional memory computing environments
#4 | 2018-12-20Instruction to cancel outstanding cache prefetches
#5 | 2018-07-19Hardware transaction transient conflict resolution
#6 | 2018-07-05Prefetching of discontiguous storage locations in anticipation of transactional execution
#7 | 2018-05-17System, method, program, and code generation unit
#8 | 2018-03-15Dynamic prediction of hardware transaction resource requirements
#9 | 2018-03-08Non-default instruction handling within transaction
#10 | 2018-03-08Enabling end of transaction detection using speculative look ahead
#11 | 2018-03-01Dynamic prediction of hardware transaction resource requirements
#12 | 2017-09-14Hardware transaction transient conflict resolution
#13 | 2017-09-14Hardware transaction transient conflict resolution
#14 | 2017-07-06Instruction to cancel outstanding cache prefetches
#15 | 2017-06-08Prefetching of discontiguous storage locations in anticipation of transactional execution
#16 | 2017-05-11Instruction stream modification for memory transaction protection
#17 | 2017-05-11Instruction stream modification for memory transaction protection
#18 | 2017-05-04Interprocessor memory status communication
#19 | 2017-05-04Interprocessor memory status communication
#20 | 2017-05-04Interprocessor memory status communication
#21 | 2017-05-04Interprocessor memory status communication
#22 | 2017-05-04Interprocessor memory status communication
#23 | 2017-02-07Interprocessor memory status communication
#24 | 2017-02-07Interprocessor memory status communication
#25 | 2017-01-03Instruction to cancel outstanding cache prefetches
#26 | 2016-12-29Non-default instruction handling within transaction
#27 | 2016-12-29Address probing for transaction
#28 | 2016-12-29Non-default instruction handling within transaction
#29 | 2016-12-29Address probing for transaction
#30 | 2016-12-22Transactional lock elision with delayed lock checking
#31 | 2016-12-08ALERTING HARDWARE TRANSACTIONS THAT ARE ABOUT TO RUN OUT OF SPACE
#32 | 2016-12-08Alerting hardware transactions that are about to run out of space
#33 | 2016-12-01Salvaging lock elision transactions with instructions to change execution type
#34 | 2016-12-01Enabling end of transaction detection using speculative look ahead
#35 | 2016-09-29Code optimization to enable and disable coalescing of memory transactions
#36 | 2016-08-25Hint instruction for managing transactional aborts in transactional memory computing environments
#37 | 2016-08-25Hint instruction for managing transactional aborts in transactional memory computing environments
#38 | 2016-08-25Using hardware transactional memory for implementation of queue operations
#39 | 2016-07-07Salvaging hardware transactions
#40 | 2016-07-07Salvaging hardware transactions
#41 | 2016-05-19System, method, program, and code generation unit
#42 | 2016-03-31Multi-granular cache management in multi-processor computing environments
#43 | 2016-01-07Salvaging lock elision transactions
#44 | 2016-01-07Salvaging lock elision transactions with instructions to change execution type
#45 | 2016-01-07Salvaging hardware transactions with instructions
#46 | 2016-01-07Salvaging hardware transactions with instructions
#47 | 2016-01-07Salvaging hardware transactions with instructions to transfer transaction execution control
#48 | 2016-01-07Methods for single-owner multi-consumer work queues for repeatable tasks
#49 | 2016-01-07Alerting hardware transactions that are about to run out of space
#50 | 2016-01-07Dynamic prediction of hardware transaction resource requirements
#51 | 2016-01-07Determining if transactions that are about to run out of resources can be salvaged or need to be aborted
#52 | 2016-01-07Code optimization to enable and disable coalescing of memory transactions
#53 | 2015-12-31Prefetching of discontiguous storage locations as part of transactional execution
#54 | 2015-12-31Prefetching of discontiguous storage locations in anticipation of transactional execution
#55 | 2015-12-31Dynamic predictor for coalescing memory transactions
#56 | 2015-12-31Prefetching of discontiguous storage locations as part of transactional execution
#57 | 2015-12-31Prefetching of discontiguous storage locations in anticipation of transactional execution
#58 | 2015-12-24Memory transaction having implicit ordering effects
#59 | 2015-12-24Using the transaction-begin instruction to manage transactional aborts in transactional memory computing environments
#60 | 2015-12-24Hint instruction for managing transactional aborts in transactional memory computing environments
#61 | 2015-12-24Memory transaction having implicit ordering effects
#62 | 2015-12-17Adaptive process for data sharing with selection of lock elision and locking
#63 | 2015-12-17Predicting the length of a transaction
#64 | 2015-12-10Salvaging hardware transactions
#65 | 2015-12-10Salvaging hardware transactions
#66 | 2015-12-10Indicating nearing the completion of a transaction
#67 | 2015-10-08Coalescing memory transactions
#68 | 2015-10-01Transactional processing based upon run-time conditions
#69 | 2015-09-03Executing instruction with threshold indicating nearing of completion of transaction
#70 | 2015-08-27Salvaging hardware transactions
#71 | 2015-08-27Salvaging hardware transactions with instructions
#72 | 2015-08-27Salvaging hardware transactions with instructions
#73 | 2015-08-27Salvaging hardware transactions
#74 | 2015-08-27Salvaging hardware transactions with instructions to transfer transaction execution control
#75 | 2015-08-27Salvaging lock elision transactions with instructions to change execution type
#76 | 2015-08-27Salvaging lock elision transactions
#77 | 2015-08-27Alerting hardware transactions that are about to run out of space
#78 | 2015-08-27Adaptive process for data sharing with selection of lock elision and locking
#79 | 2015-08-27Using the transaction-begin instruction to manage transactional aborts in transactional memory computing environments
#80 | 2015-08-27COMMITTING HARDWARE TRANSACTIONS THAT ARE ABOUT TO RUN OUT OF RESOURCE
#81 | 2015-08-27Suppressing aborting a transaction beyond a threshold execution duration based on the predicted duration
#82 | 2015-08-27Dynamic prediction of concurrent hardware transactions resource requirements and allocation
#83 | 2015-08-27Hint instruction for managing transactional aborts in transactional memory computing environments
#84 | 2015-06-18Dynamic predictor for coalescing memory transactions
#85 | 2015-06-18Code optimization to enable and disable coalescing of memory transactions
#86 | 2015-06-18Coalescing memory transactions
#87 | 2015-03-26Multi-granular cache management in multi-processor computing environments
#88 | 2015-03-26Centralized management of high-contention cache lines in multi-processor computing environments
#89 | 2015-03-26Managing high-coherence-miss cache lines in multi-processor computing environments
#90 | 2015-03-26Identifying high-conflict cache lines in transactional memory computing environments
#91 | 2015-03-26Managing high-conflict cache lines in transactional memory computing environments
#92 | 2015-03-12Signal interrupts in a transactional memory system
#93 | 2015-03-12Signal interrupts in a transactional memory system
#94 | 2014-12-04Using hardware transactional memory for implementation of queue operations
#95 | 2014-12-04Using hardware transactional memory for implementation of queue operations
#96 | 2014-11-27LINKED LIST FOR LOCK-FREE MEMORY ALLOCATION
#97 | 2014-11-27LINKED LIST FOR LOCK-FREE MEMORY ALLOCATION
#98 | 2014-10-02Transactional lock elision with delayed lock checking
#99 | 2014-10-02Transactional lock elision with delayed lock checking
#100 | 2013-06-20Code section optimization by removing memory barrier instruction and enclosing within a transaction that employs hardware transaction memory
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