Austin, Texas
United States
169
2019-08-29
The entities that hold a legal rights for patent applications filed by inventor Williams Derek E.:
Derek E. Williams from Austin, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Adaptively enabling and disabling snooping bus commands
#2 | 2019-07-18Remote node broadcast of requests in a multinode data processing system
#3 | 2019-07-18Remote node broadcast of requests in a multinode data processing system
#4 | 2019-07-18Remote node broadcast of requests in a multinode data processing system
#5 | 2019-06-20Coherence protocol providing speculative coherence response to directory probe
#6 | 2019-05-30Accelerator memory coherency with single state machine
#7 | 2018-12-27Efficient enforcement of barriers with respect to memory move sequences
#8 | 2018-12-06Temporarily favoring selection of store requests from one of multiple store queues for issuance to a bank of a banked cache
#9 | 2018-12-06Banked cache temporarily favoring selection of store requests from one of multiple store queues
#10 | 2018-12-06Multicopy atomic store operation in a data processing system
#11 | 2018-12-06Multicopy atomic store operation in a data processing system
#12 | 2018-11-15Implementing barriers to efficiently support cumulativity in a weakly ordered memory system
#13 | 2018-11-08Speculatively performing memory move requests with respect to a barrier
#14 | 2018-06-14Simulation employing level-dependent multitype events
#15 | 2018-02-22Memory move supporting speculative acquisition of source and destination data granules including copy-type and paste-type instructions
#16 | 2018-02-22Adaptively enabling and disabling snooping bus commands
#17 | 2018-02-22Memory move instruction sequence including a stream of copy-type and paste-type instructions
#18 | 2018-02-22Speculatively performing memory move requests with respect to a barrier
#19 | 2018-02-22Memory move instruction sequence enabling software control
#20 | 2018-02-22Migration of memory move instruction sequences between hardware threads
#21 | 2018-02-22Efficient enforcement of barriers with respect to memory move sequences
#22 | 2018-02-22Memory access in a data processing system utilizing copy and paste instructions
#23 | 2018-02-22Memory move instruction sequence targeting a memory-mapped device
#24 | 2017-11-02Implementing barriers to efficiently support cumulativity in a weakly-ordered memory system
#25 | 2017-11-02Implementing barriers to efficiently support cumulativity in a weakly-ordered memory system
#26 | 2017-10-12Early freeing of a snoop machine of a data processing system prior to completion of snoop processing for an interconnect operation
#27 | 2017-10-12Decreasing the data handoff interval for a reserved cache line based on an early indication of a systemwide coherence response
#28 | 2017-10-12Decreasing the data handoff interval in a multiprocessor data processing system based on an early indication of a systemwide coherence response
#29 | 2017-10-10Translation entry invalidation in a multithreaded data processing system
#30 | 2017-09-26Translation entry invalidation in a multithreaded data processing system
#31 | 2017-06-22Translation entry invalidation in a multithreaded data processing system
#32 | 2017-06-22Translation entry invalidation in a multithreaded data processing system
#33 | 2017-06-22Translation entry invalidation in a multithreaded data processing system
#34 | 2017-06-22Translation entry invalidation in a multithreaded data processing system
#35 | 2017-06-22Translation entry invalidation in a multithreaded data processing system
#36 | 2017-06-08Addressing topology specific replicated bus units
#37 | 2017-05-30Injection of at least a partial cache line in a private multilevel cache hierarchy
#38 | 2017-03-02Expedited servicing of store operations in a data processing system
#39 | 2017-03-02Expedited servicing of store operations in a data processing system
#40 | 2017-03-02Expedited servicing of store operations in a data processing system
#41 | 2017-03-02Expedited servicing of store operations in a data processing system
#42 | 2017-03-02Expedited servicing of store operations in a data processing system
#43 | 2017-03-02Expedited servicing of store operations in a data processing system
#44 | 2017-03-02Expedited servicing of store operations in a data processing system
#45 | 2017-03-02Expedited servicing of store operations in a data processing system
#46 | 2017-02-21Random number generation security
#47 | 2017-02-21Translation entry invalidation in a multithreaded data processing system
#48 | 2017-02-21Techniques for addressing topology specific replicated bus units
#49 | 2017-02-16Techniques for implementing barriers to efficiently support cumulativity in a weakly-ordered memory system
#50 | 2017-01-05Transactional storage accesses supporting differing priority levels
#51 | 2017-01-05Transactional storage accesses supporting differing priority levels
#52 | 2016-12-27Topology specific replicated bus unit addressing in a data processing system
#53 | 2016-12-06Topology specific replicated bus unit addressing in a data processing system
#54 | 2016-08-16Techniques for improving random number generation security
#55 | 2016-03-03Cache backing store for transactional memory
#56 | 2016-03-03Cache backing store for transactional memory
#57 | 2015-12-24Memory transaction having implicit ordering effects
#58 | 2015-12-24Memory transaction having implicit ordering effects
#59 | 2015-11-19Managing memory transactions in a distributed shared memory system supporting caching above a point of coherency
#60 | 2015-11-19Managing memory transactions in a distributed shared memory system supporting caching above a point of coherency
#61 | 2015-10-08Techniques for implementing barriers to efficiently support cumulativity in a weakly-ordered memory system
#62 | 2015-10-08Techniques for implementing barriers to efficiently support cumulativity in a weakly-ordered memory system
#63 | 2015-09-24Adaptively enabling and disabling snooping fastpath commands
#64 | 2015-08-27Synchronizing access to data in shared memory
#65 | 2015-08-27Synchronizing access to data in shared memory
#66 | 2015-08-27Managing speculative memory access requests in the presence of transactional storage accesses
#67 | 2015-08-27Managing speculative memory access requests in the presence of transactional storage accesses
#68 | 2015-08-13Adaptively enabling and disabling snooping fastpath commands
#69 | 2015-06-11Bypassing a store-conditional request around a store queue
#70 | 2015-06-11Bypassing a store-conditional request around a store queue
#71 | 2015-02-19Management of transactional memory access requests by a cache memory
#72 | 2015-02-19Protecting the footprint of memory transactions from victimization
#73 | 2015-02-19PROTECTING THE FOOTPRINT OF MEMORY TRANSACTIONS FROM VICTIMIZATION
#74 | 2015-02-19Management of transactional memory access requests by a cache memory
#75 | 2014-02-13Interaction of transactional storage accesses with other atomic semantics
#76 | 2014-02-13Transaction check instruction for memory transactions
#77 | 2014-02-13Transaction check instruction for memory transactions
#78 | 2014-02-06Nested rewind only and non rewind only transactions in a data processing system supporting transactional storage accesses
#79 | 2014-02-06Rewind only transactions in a data processing system supporting transactional storage accesses
#80 | 2014-01-09Ensuring causality of transactional storage accesses interacting with non-transactional storage accesses
#81 | 2014-01-09ENSURING CAUSALITY OF TRANSACTIONAL STORAGE ACCESSES INTERACTING WITH NON-TRANSACTIONAL STORAGE ACCESSES
#82 | 2013-10-03Data cache block deallocate requests in a multi-level cache hierarchy
#83 | 2013-10-03Data cache block deallocate requests
#84 | 2013-10-03Data cache block deallocate requests in a multi-level cache hierarchy
#85 | 2013-10-03Data cache block deallocate requests
#86 | 2013-08-08Improving processor performance for instruction sequences that include barrier instructions
#87 | 2013-08-08Processor performance improvement for instruction sequences that include barrier instructions
#88 | 2013-08-08Forward progress mechanism for stores in the presence of load contention in a system favoring loads by state alteration
#89 | 2013-08-08Forward progress mechanism for stores in the presence of load contention in a system favoring loads
#90 | 2013-08-08Forward progress mechanism for stores in the presence of load contention in a system favoring loads by state alteration
#91 | 2013-08-08Forward progress mechanism for stores in the presence of load contention in a system favoring loads
#92 | 2013-01-10Using Hardware Transaction Primitives for Implementing Non-Transactional Escape Actions Inside Transactions
#93 | 2012-12-20Aggregate data processing system having multiple overlapping synthetic computers
#94 | 2012-11-22Facilitating data coherency using in-memory tag bits and tag test instructions
#95 | 2012-11-22Facilitating data coherency using in-memory tag bits and faulting stores
#96 | 2012-11-22Facilitating data coherency using in-memory tag bits and tag test instructions
#97 | 2012-10-18Performing a partial cache line storage-modifying operation based upon a hint
#98 | 2012-08-16Cache-based speculation of stores following synchronizing operations
#99 | 2012-08-09Memory coherence directory supporting remotely sourced requests of nodal scope
#100 | 2012-08-09Selective cache-to-cache lateral castouts
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