Inventor profile of:

Frédéric Bancel

City:

Lamanon

Country:

France

Published Applications:

24

Last publication date:

2011-09-01

Top Assignees for applications by Frédéric Bancel

The entities that hold a legal rights for patent applications filed by inventor Bancel Frédéric:

Recent patent applications by Bancel Frédéric

Frédéric Bancel from Lamanon, FR has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2011-09-01
US20110214012A1
Physics

Secured coprocessor comprising an event detection circuit

#2 | 2011-05-26
US20110126065A1
Physics

Microprocessor comprising signature means for detecting an attack by error injection

#3 | 2011-02-03
US20110029828A1
Physics

Fault injection detector in an integrated circuit

#4 | 2009-10-08
US20090254782A1
Physics

Method and device for detecting an erroneous jump during program execution

#5 | 2009-06-25
US20090164858A1
Physics

Protecting an integrated circuit test mode

#6 | 2008-11-27
US20080294880A1
Physics

CUSTOMIZATION OF A MICROPROCESSOR AND DATA PROTECTION METHOD

#7 | 2008-09-25
US20080231325A1
Physics

Method for checking the integrity of a clock tree

#8 | 2008-09-18
US20080228989A1
Physics

Method and device for securing the reading of a memory

#9 | 2008-08-28
US20080208497A1
Physics

Method and device for checking the integrity of a logic signal, in particular a clock signal

#10 | 2008-08-14
US20080191741A1
Physics

Integrated circuit having configurable cells and a secured test mode

#11 | 2008-01-24
US20080022174A1
Physics

Electronic circuit comprising a test mode secured by insertion of decoy data in the test chain, associated method

#12 | 2007-11-08
US20070257701A1
Physics

Integrated circuit comprising a test mode secured by the use of an identifier, and associated method

#13 | 2007-10-04
US20070234156A1
Physics

Electronic circuit comprising a test mode secured by the breaking of a test chain, and associated electronic circuit

#14 | 2007-02-22
US20070043986A1
Physics

Method for testing an electronic circuit comprising a test mode secured by the use of a signature, and associated electronic circuit

#15 | 2007-02-08
US20070033467A1
Physics

Method and device for protecting a memory against attacks by error injection

#16 | 2007-02-08
US20070033463A1
Physics

Integrated circuit comprising a test mode secured by detection of the state of a control signal

#17 | 2006-11-23
US20060265570A1
Physics

Secured coprocessor comprising means for preventing access to a unit of the coprocessor

#18 | 2006-11-16
US20060259673A1
Physics

Secured coprocessor comprising an event detection circuit

#19 | 2006-08-31
US20060195723A1
Physics

Securing the test mode of an integrated circuit

#20 | 2005-12-01
US20050268163A1
Physics

Microprocessor comprising signature means for detecting an attack by error injection

#21 | 2005-11-10
US20050251708A1
Physics

Microprocessor comprising error detection means protected against an attack by error injection

#22 | 2005-08-04
US20050172185A1
Physics

Integrated circuit comprising a test mode secured by initialization of the test mode

#23 | 2005-08-04
US20050172184A1
Physics

Method of securing the test mode of an integrated circuit via intrusion detection

#24 | 2005-08-04
US20050169076A1
Physics

Protecting an integrated circuit test mode

InventorID:

3340861