Hsien-Wei Chen

Semiconductor chip having different conductive pad widths and method of making layout for same

Wafer having pad structure

Chip package and method of manufacturing the same

Semiconductor devices with ball strength improvement

Methods of making integrated circuits

Structure and method of forming a pad structure having enhanced reliability

Semiconductor wafer with assisting dicing structure and dicing method thereof

Chip package and method of manufacturing the same

Method of making a semiconductor device having a post-passivation interconnect structure

Package on package structure

Bump structure design for stress reduction

Post-passivation interconnect structure

Semiconductor device with bump structure on an interconncet structure

Structure for reducing integrated circuit corner peeling

Methods and apparatus of under bump metallization in packaging semiconductor devices

Semiconductor device with seal ring with embedded decoupling capacitor

Methods of and semiconductor devices with ball strength improvement

Wafer-level chip scale package with re-workable underfill

Post-passivation interconnect structure

Wafer level chip scale package and method of manufacturing the same

Integrated circuits with leakage current test structure

Bond pad structure to reduce bond pad corrosion

Method and device for circuit routing by way of under-bump metallization

Mechanisms for marking the orientation of a sawed die

Uniformity control for IC passivation structure

Structure designs and methods for integrated circuit alignment

Integrated circuit with test circuit

Reinforcement structure for flip-chip packaging

Bond pad structure

Increasing dielectric strength by optimizing dummy metal distribution

Seal ring structure for integrated circuit chips

Method and apparatus of fabricating a pad structure for a semiconductor device

Structure to reduce etching residue

Grounded seal ring structure in semiconductor devices

Semiconductor component having a second passivation layer having a first opening exposing a bond pad and a plurality of second openings exposing a top surface of an underlying first passivation layer

Measurement of electrical and mechanical characteristics of low-K dielectric in a semiconductor device

Semiconductor chip having different pad width to UBM width ratios and method of manufacturing the same

Pad structure having contact bars extending into substrate and wafer having the pad structure

Package-on-package structures with reduced bump bridging

Reducing delamination between an underfill and a buffer layer in a bond structure

Seal ring structure in semiconductor devices

Semiconductor test pad structures

Probe pad on a corner stress relief region in a semiconductor chip

Probe pad on a corner stress relief region in a semiconductor chip

Dummy pattern in wafer backside routing

Radiate under-bump metallization structure for semiconductor devices

Corner stress release structure design for increasing circuit routing areas

Heat spreader structures in scribe lines

Pad structure for semiconductor devices

Structure for integrated circuit alignment

Chip design with robust corner bumps

Integrated circuit with protective structure

Solving via-misalignment issues in interconnect structures having air-gaps

Package structures

Bond pad design for reducing the effect of package stress

Package structure and method for reducing dielectric layer delamination

Process for improving the reliability of interconnect structures and resulting structure

Structure and method of forming a pad structure having enhanced reliability

Bump pad structure

Dicing structures for semiconductor substrates and methods of fabrication thereof

Structure for improving die saw quality

Scribe line metal structure

Underbump metallization structure

Robust TSV structure

Parametric testline with increased test pattern areas

Double solid metal pad with reduced area

Heat spreader structures in scribe lines

Pad structure having a metalized region and a non-metalized region

Semiconductor test pad structures

Method for mechanical stress enhancement in semiconductor devices

Structure for reducing integrated circuit corner peeling

Protective seal ring for preventing die-saw induced stress

Semiconductor interconnect air gap formation process

Backend interconnect scheme with middle dielectric layer having improved strength

Bond pad structure

Wafer scribe line structure for improving IC reliability

Solving via-misalignment issues in interconnect structures having air-gaps

Bond pad design for fine pitch wire bonding

Method and structure for increased wire bond density in packages for semiconductor chips

Parametric testline with increased test pattern areas

Structure design for minimizing on-chip interconnect inductance

Metal e-fuse structure design

Test structure for seal ring quality monitor

Pad structure design with reduced density

Process for improving the reliability of interconnect structures and resulting structure

Increasing dielectric constant in local regions for the formation of capacitors

PAD structure and method of testing

Integrated stress relief pattern and registration structure

Semiconductor device structure and methods of manufacturing the same

Metal electrical fuse structure

System in package (SIP) structure

Dummy structures extending from seal ring into active circuit area of integrated circuit chip

Method and apparatus for enhanced CMP planarization using surrounded dummy design

Design structure for coupling noise prevention

Bond pad structure for integrated circuit chip

Integrated stress relief pattern and registration structure