Meridian, Idaho
United States
38
2018-06-28
The entities that hold a legal rights for patent applications filed by inventor Johnson Christopher S.:
Christopher S. Johnson from Meridian, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Apparatuses and methods for selective determination of data error repair
#2 | 2017-12-07Apparatuses and methods for selective determination of data error repair
#3 | 2014-05-08Adjustable Byte Lane Offset For Memory Module to Reduce Skew
#4 | 2013-11-14Method and apparatus for detecting communication errors on a bus
#5 | 2013-01-10Method and apparatus for detecting communication errors on a bus
#6 | 2012-08-02Dynamically setting burst length of double data rate memory device by applying signal to at least one external pin during a read or write transaction
#7 | 2012-03-29Method and apparatus for detecting communication errors on a bus
#8 | 2012-02-23Adjustable byte lane offset for memory module to reduce skew
#9 | 2012-01-05Dynamically setting burst length of double data rate memory device by applying signal to at least one external pin during a read or write transaction
#10 | 2011-02-17Memory device and method having low-power, high write latency mode and high-power, low write latency mode and/or independently selectable write latency
#11 | 2010-12-30SYSTEM AND METHOD FOR PROVIDING CONFIGURABLE LATENCY AND/OR DENSITY IN MEMORY DEVICES
#12 | 2010-10-14Method and apparatus for detecting communication errors on a bus
#13 | 2010-04-22User selectable banks for DRAM
#14 | 2009-12-10Dynamically setting burst length of double data rate memory device by applying signal to at least one external pin during a read or write transaction
#15 | 2009-11-05Dynamically setting burst length of double data rate memory device by applying signal to at least one external pin during a read or write transaction
#16 | 2009-03-12Memory device and method having low-power, high write latency mode and high-power, low write latency mode and/or independently selectable write latency
#17 | 2009-02-26Adjustable byte lane offset for memory module to reduce skew
#18 | 2007-11-22Memory device and method having low-power, high write latency mode and high-power, low write latency mode and/or independently selectable write latency
#19 | 2007-10-18User selectable banks for DRAM
#20 | 2007-08-16Selectable clock unit
#21 | 2007-04-10User selectable banks for DRAM
#22 | 2007-02-13Controlling multiple signal polarity in a semiconductor device
#23 | 2007-02-08Method and apparatus for detecting communication errors on a bus
#24 | 2006-12-12Dynamically setting burst length of memory device by applying signal to at least one external pin during a read or write transaction
#25 | 2006-11-23Controlling multiple signal polarity in a semiconductor device
#26 | 2006-11-09Adjustable byte lane offset for memory module to reduce skew
#27 | 2006-07-13Memory device and method having low-power, high write latency mode and high-power, low write latency mode and/or independently selectable write latency
#28 | 2006-05-25Synchronous DRAM with selectable internal prefetch size
#29 | 2006-04-27Dynamically setting burst length of memory device by applying signal to at least one external pin during a read or write transaction
#30 | 2006-03-23Selectable clock input
#31 | 2006-01-24Selectable clock input
#32 | 2005-08-23Memory device and method having low-power, high write latency mode and high-power, low write latency mode and/or independently selectable write latency
#33 | 2005-06-09Memory device and method having low-power, high write latency mode and high-power, low write latency mode and/or independently selectable write latency
#34 | 2005-06-02Memory device and method having low-power, high write latency mode and high-power, low write latency mode and/or independently selectable write latency
#35 | 2005-05-17Synchronous DRAM with selectable internal prefetch size
#36 | 2005-04-21Synchronous DRAM with selectable internal prefetch size
#37 | 2005-04-21Methods and apparatuses for transferring heat from microelectronic device modules
#38 | 2005-01-06Memory module with integrated bus termination
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