Austin, Texas
United States
53
2018-11-15
The entities that hold a legal rights for patent applications filed by inventor Olson Christopher H.:
Christopher H. Olson from Austin, US has applied for patents for these inventions. The list has both pending applications and granted patents:
OPTIMIZED INTEGER DIVISION CIRCUIT
#2 | 2017-11-09Floating point unit with support for variable length numbers
#3 | 2017-02-16Processing fixed and variable length numbers
#4 | 2015-12-31IMPLEMENTATION FOR A HIGH PERFORMANCE BCD DIVIDER
#5 | 2015-10-15Processing fixed and variable length numbers
#6 | 2015-09-10Floating point unit with support for variable length numbers
#7 | 2013-07-11Division unit with normalization circuit and plural divide engines for receiving instructions when divide engine availability is indicated
#8 | 2013-05-30STORING A TARGET ADDRESS OF A CONTROL TRANSFER INSTRUCTION IN AN INSTRUCTION FIELD
#9 | 2012-11-15Suppressing branch prediction information update by branch instructions in incorrect speculative execution path
#10 | 2012-11-15Associating tag to branch instruction to access array storing predicted target addresses for page crossing targets for comparison with resolved address at execution stage
#11 | 2012-10-11Pipelined divide circuit for small operand sizes
#12 | 2012-09-13System and method of bypassing unrounded results in a multiply-add pipeline unit
#13 | 2012-08-30Processor pipeline which implements fused and unfused multiply-add instructions
#14 | 2012-08-23INSTRUCTION SUPPORT FOR PERFORMING STREAM CIPHER
#15 | 2012-06-05Handling multi-cycle integer operations for a multi-threaded processor
#16 | 2012-04-12Execution unit for performing the data encryption standard
#17 | 2012-03-08Register error correction of speculative data in an out-of-order processor
#18 | 2011-12-01Processor and method providing instruction support for instructions that utilize multiple register windows
#19 | 2011-11-10Instruction support for performing montgomery multiplication
#20 | 2011-11-10Thread fairness on a multi-threaded processor with multi-cycle cryptographic operations
#21 | 2011-09-22Apparatus and method for implementing instruction support for performing a cyclic redundancy check (CRC)
#22 | 2011-05-10Method for selecting between divide instructions associated with respective threads in a multi-threaded processor
#23 | 2011-04-21HARDWARE KASUMI CYPHER WITH HYBRID SOFTWARE INTERFACE
#24 | 2011-04-14Apparatus and method for local operand bypassing for cryptographic instructions
#25 | 2011-03-31Accessing a multibank register file using a thread identifier
#26 | 2010-12-30INSTRUCTIONS FOR PERFORMING DATA ENCRYPTION STANDARD (DES) COMPUTATIONS USING GENERAL-PURPOSE REGISTERS
#27 | 2010-12-23Processor and method for implementing instruction support for multiplication of large operands
#28 | 2010-10-21Mechanism for handling unfused multiply-accumulate accrued exception bits in a processor
#29 | 2010-10-07Methods and mechanisms to support multiple features for a number of opcodes
#30 | 2010-09-30Processor and method for implementing instruction support for hash algorithms
#31 | 2010-09-30APPARATUS AND METHOD FOR IMPLEMENTING INSTRUCTION SUPPORT FOR THE ADVANCED ENCRYPTION STANDARD (AES) ALGORITHM
#32 | 2010-09-30Apparatus and method for implementing instruction support for the camellia cipher algorithm
#33 | 2010-09-30Apparatus and method for implementing hardware support for denormalized operands for floating-point divide operations
#34 | 2010-09-30APPARATUS AND METHOD FOR IMPLEMENTING INSTRUCTION SUPPORT FOR THE KASUMI CIPHER ALGORITHM
#35 | 2010-09-30Apparatus and method for implementing instruction support for the data encryption standard (DES) algorithm
#36 | 2010-09-14Enabling on-chip features via efuses
#37 | 2010-05-18Apparatus and method for implementing a hash algorithm word buffer
#38 | 2010-05-04Apparatus and method for cryptographic key expansion
#39 | 2010-03-23Apparatus and method for implementing a unified hash algorithm pipeline
#40 | 2009-11-17Processor including general-purpose and cryptographic functionality in which cryptographic operations are visible to user-specified software
#41 | 2009-10-01Processor which implements fused and unfused multiply-add instructions in a pipelined manner
#42 | 2009-08-04Apparatus and method for implementing a block cipher algorithm
#43 | 2009-08-04Out-of-order memory transactions in a fine-grain multithreaded/multi-core processor
#44 | 2009-03-05Register error correction of speculative data in an out-of-order processor
#45 | 2009-01-13Apparatus and method to support pipelining of differing-latency instructions in a multithreaded processor
#46 | 2008-10-28Execution unit for performing the data encryption standard
#47 | 2008-10-14Apparatus and method for reducing execution latency of floating point operations having special case operands
#48 | 2008-01-15Synchronization primitives for flexible scheduling of functional unit operations
#49 | 2007-05-08Register window management using first pipeline to change current window and second pipeline to read operand from old window and write operand to new window
#50 | 2006-08-29Partitioned shifter for single instruction stream multiple data stream (SIMD) operations
#51 | 2006-06-15Low latency integer divider and integration with floating point divider and method
#52 | 2006-01-05Thread-based clock enabling in a multi-threaded processor
#53 | 2005-01-13Method and apparatus for fast RC4-like encryption
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