Rochester, Minnesota
United States
23
2023-09-28
The entities that hold a legal rights for patent applications filed by inventor Fredrickson Mark S.:
Mark S. Fredrickson from Rochester, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Sound-based presentation attack detection
#2 | 2022-06-09Authorizing uses of goods or services using bonding agreement
#3 | 2021-05-20Authenticating digital recordings
#4 | 2020-09-24Network-based authorization for disconnected devices
#5 | 2020-02-06Analysis of verification parameters for training reduction
#6 | 2019-08-29Authenticating digital recordings
#7 | 2019-07-11Techniques for faster loading of data for accelerators
#8 | 2016-11-22Communicating in an integrated circuit using hardware-managed virtual channels
#9 | 2015-12-10Delayed execution of program code on multiple processors
#10 | 2014-07-10VARIABLE DEPTH INSTRUCTION FIFOS TO IMPLEMENT SIMD ARCHITECTURE
#11 | 2013-07-11Methods and systems with delayed execution of multiple processors
#12 | 2009-07-09Heuristic clustering of circuit elements in a circuit design
#13 | 2008-12-11TRADING PROPENSITY-BASED CLUSTERING OF CIRCUIT ELEMENTS IN A CIRCUIT DESIGN
#14 | 2008-06-12AUTOMATIC BACK ANNOTATION OF A FUNCTIONAL DEFINITION OF AN INTEGRATED CIRCUIT DESIGN BASED UPON PHYSICAL LAYOUT
#15 | 2008-06-05Method, apparatus and computer program product for implementing scan-chain-specific control signals as part of a scan chain
#16 | 2008-02-28Methods and apparatus for reducing command processing latency while maintaining coherence
#17 | 2007-11-08Trading propensity-based clustering of circuit elements in a circuit design
#18 | 2007-08-09Automatic back annotation of a functional definition of an integrated circuit design based upon physical layout
#19 | 2007-08-09Heuristic clustering of circuit elements in a circuit design
#20 | 2007-08-09Methods and apparatus for reducing command processing latency while maintaining coherence
#21 | 2007-07-19Method, apparatus and computer program product for designing logic scan chains for matching gated portions of a clock tree
#22 | 2007-05-03Method, apparatus and computer program product for implementing scan-chain-specific control signals as part of a scan chain
#23 | 2007-03-29Fair hierarchical arbiter
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