Inventor profile of:

Jeffrey A. Sabrowski

City:

Leander, Texas

Country:

United States

Published Applications:

17

Last publication date:

2018-03-08

Top Assignees for applications by Jeffrey A. Sabrowski

The entities that hold a legal rights for patent applications filed by inventor Sabrowski Jeffrey A.:

Recent patent applications by Sabrowski Jeffrey A.

Jeffrey A. Sabrowski from Leander, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2018-03-08
US20180067874A1
Physics

System for securing contents of removable memory

#2 | 2016-01-28
US20160027494A1
Physics

Prioritizing refreshes in a memory device

#3 | 2015-10-01
US20150278086A1
Physics

Implementing enhanced reliability of systems utilizing dual port DRAM

#4 | 2015-10-01
US20150278005A1
Physics

Implementing enhanced reliability of systems utilizing dual port DRAM

#5 | 2015-08-13
US20150228328A1
Physics

Reference voltage modification in a memory device

#6 | 2015-07-30
US20150213854A1
Physics

Implementing simultaneous read and write operations utilizing dual port DRAM

#7 | 2015-07-30
US20150213853A1
Physics

Implementing simultaneous read and write operations utilizing dual port DRAM

#8 | 2015-06-25
US20150178147A1
Physics

Self monitoring and self repairing ECC

#9 | 2015-05-07
US20150127899A1
Physics

Memory device for interruptible memory refresh

#10 | 2015-05-07
US20150127898A1
Physics

System and memory controller for interruptible memory refresh

#11 | 2014-11-13
US20140334225A1
Physics

Prioritizing refreshes in a memory device

#12 | 2014-11-13
US20140334224A1
Physics

Reference voltage modification in a memory device

#13 | 2014-10-23
US20140317473A1
Physics

Implementing ECC redundancy using reconfigurable logic blocks

#14 | 2014-09-25
US20140289488A1
Physics

System for securing contents of removable memory

#15 | 2014-09-04
US20140250340A1
Physics

Self monitoring and self repairing ECC

#16 | 2014-03-06
US20140068322A1
Physics

Implementing DRAM command timing adjustments to alleviate DRAM failures

#17 | 2013-07-11
US20130179724A1
Physics

Implementing enhanced hardware assisted DRAM repair using a data register for DRAM repair selectively provided in a DRAM module

InventorID:

338251 ⎘