Ravi K. Arimilli

Management of process-to-process communication requests

Management of process-to-process communication requests

ENVIRONMENTAL CONTROL OF LIQUID COOLED ELECTRONICS

Performing setup operations for receiving different amounts of data while processors are performing message passing interface tasks

Performing a partial cache line storage-modifying operation based upon a hint

Dynamic monitoring of ability to reassemble streaming data across multiple channels based on history

Programming language exposing idiom calls to a programming idiom accelerator

Hardware wake-and-go mechanism with look-ahead polling

Wake-and-go mechanism for a data processing system

Central repository for wake-and-go mechanism

Wake-and-go mechanism with prioritization of threads

Compiler providing idiom to idiom accelerator

Hardware wake-and-go mechanism and content addressable memory with instruction pre-fetch look-ahead to detect programming idioms

Look-ahead wake-and-go engine with speculative execution

Programming idiom accelerator to examine pre-fetched instruction streams for multiple processors

Thread partitioning in a multi-core environment

General purpose register cloning

Wake-and-go mechanism with exclusive system bus response

Wake-and-go mechanism with system bus response

Varying a data prefetch size based upon data usage

Wake-and-go mechanism with system address bus transaction master

Speculative popcount data creation

Migrating sleeping and waking threads between wake-and-go mechanisms in a multiple processor data processing system

User level message broadcast mechanism in distributed computing environment

Remote update programming idiom accelerator with allocated processor resources

Techniques for cache injection in a processor system from a remote node

Dynamic runtime modification of array layout for offset

Programming idiom accelerator for remote update

Complex remote update programming idiom accelerator

Remote asynchronous data mover

Environmental control of liquid cooled electronics

Dynamic monitoring of ability to reassemble streaming data across multiple channels based on history

Techniques for cache injection in a processor system based on a shared state

Consolidating file system backend operations with access of data

Virtual barrier synchronization cache

Virtual barrier synchronization cache castout election

Management of application to I/O device communication requests between data processing systems

Management of process-to-process intra-cluster communication requests

Management of application to application communication requests between data processing systems

Management of process-to-process inter-cluster communication requests

Reassembling streaming data across multiple packetized communication channels

Computation table for block computation

Operand data structure for block computation

Specifying an addressing relationship in an operand data structure

Block driven computation with an address generation accelerator

Block driven computation using a caching policy specified in an operand data structure

Physical interface macros (PHYS) supporting heterogeneous electrical properties

Supporting multiple high bandwidth I/O controllers on a single chip

Techniques for cache injection in a processor system responsive to a specific instruction sequence

Techniques for cache injection in a processor system with replacement policy position modification

Techniques for cache injection in a processor system using a cache injection instruction

Techniques for cache injection in a processor system

Convergence of air water cooling of an electronics rack and a computer room in a single unit

Dynamic segment sparing and repair in a memory system

Wake-and-go mechanism with dynamic allocation in hardware private array

CAM-based wake-and-go snooping engine for waking a thread put to sleep for spinning on a target address lock

Wake-and-go mechanism with software save of thread state

Wake-and-go mechanism with hardware private array

Use of a helper thread to asynchronously compute incoming data

Helper thread for pre-fetching data

Hardware wake-and-go mechanism for a data processing system

Wake-and-go mechanism with data monitoring

Wake-and-go mechanism with data exclusivity

Termination of in-flight asynchronous memory move

Binding a process to a special purpose processing element having characteristics of a processor

Sourcing differing amounts of prefetch data in response to data prefetch requests

Completion of asynchronous memory move in the presence of a barrier operation

Partial cache line accesses based on memory access patterns

Dynamic routing based on information of not responded active source requests quantity received in broadcast heartbeat signal and stored in local data structure for other processor chips

Performing dynamic request routing based on broadcast queue depths

System and Method for Data Processing Using a Low-Cost Two-Tier Full-Graph Interconnect Architecture

Asynchronous memory move across physical nodes with dual-sided communication

Full virtualization of resources across an IP interconnect using page frame table

Full virtualization of resources across an IP interconnect

Techniques for indirect data prefetching

Data prefetching using indirect addressing

Launching multiple concurrent memory moves via a fully asynchronoous memory mover

Handling of address conflicts during asynchronous memory move operations

Mechanisms for communicating with an asynchronous memory mover to perform AMM operations

Reporting of partially performed memory move

Performing an asynchronous memory move (AMM) via execution of AMM store instruction within the instruction set architecture

Fully asynchronous memory mover

Method and apparatus for handling multiple memory requests within a multiprocessor system

Processing Units Within a Multiprocessor System Adapted to Support Memory Locks

Host fabric interface (HFI) to perform global shared memory (GSM) operations

Specialized memory move barrier operations

Method and Apparatus for Supporting Low-Overhead Memory Locks Within a Multiprocessor System

Dynamic selection of a memory access size

Interconnect operation indicating acceptability of partial data delivery

Cache management for partial cache line operations

Claiming coherency ownership of a partial cache line of data

DATA PROCESSING SYSTEM, PROCESSOR AND METHOD THAT SUPPORT A TOUCH OF A PARTIAL CACHE LINE OF DATA

Method for enabling direct prefetching of data during asychronous memory move operation

Techniques for multi-level indirect data prefetching

Techniques for prediction-based indirect data prefetching

Techniques for data prefetching using indirect addressing with offset

Varying an amount of data retrieved from memory based upon an instruction hint

Cache management during asynchronous memory move operations

Issuing global shared memory operations via direct cache injection to a host fabric interface

Partial cache line storage-modifying operation based upon a hint