Peekskill, New York
United States
20
2011-11-10
The entities that hold a legal rights for patent applications filed by inventor Henson William K.:
William K. Henson from Peekskill, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Efuse containing sige stack
#2 | 2011-06-23Formation of improved SOI substrates using bulk semiconductor wafers
#3 | 2010-01-21High performance stress-enhance MOSFET and method of manufacture
#4 | 2009-02-12Formation of improved SOI substrates using bulk semiconductor wafers
#5 | 2008-08-14Stressed SOI FET having tensile and compressive device regions
#6 | 2008-07-17eFuse containing SiGe stack
#7 | 2008-07-17Method of forming stressed SOI FET having doped glass box layer using sacrificial stressed layer
#8 | 2008-06-26Scalable strained FET device and method of fabricating the same
#9 | 2008-03-06Semiconductor structure with enhanced performance using a simplified dual stress liner configuration
#10 | 2008-02-28SEMICONDUCTOR STRUCTURE INCLUDING MULTIPLE STRESSED LAYERS
#11 | 2008-01-31Fully Silicided Gate Electrodes and Method of Making the Same
#12 | 2007-11-29Formation of improved SOI substrates using bulk semiconductor wafers
#13 | 2007-11-20Fully silicided gate electrodes and method of making the same
#14 | 2007-11-01Silicide gate field effect transistors and methods for fabrication thereof
#15 | 2007-11-01High performance stress-enhance MOSFET and method of manufacture
#16 | 2007-11-01High performance stress-enhance MOSFET and method of manufacture
#17 | 2007-10-11CMOS process with Si gates for nFETs and SiGe gates for pFETs
#18 | 2007-10-04Dual metal integration scheme based on full silicidation of the gate electrode
#19 | 2007-09-13LASER SURFACE ANNEALING OF ANTIMONY DOPED AMORPHIZED SEMICONDUCTOR REGION
#20 | 2007-05-31METHODS TO FORM HETEROGENEOUS SILICIDES/GERMANIDES IN CMOS TECHNOLOGY
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