Inventor profile of:

Tab A. STEPHENS

City:

Austin, Texas

Country:

United States

Published Applications:

26

Last publication date:

2015-07-30

Top Assignees for applications by Tab A. STEPHENS

The entities that hold a legal rights for patent applications filed by inventor STEPHENS Tab A.:

Recent patent applications by STEPHENS Tab A.

Tab A. STEPHENS from Austin, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2015-07-30
US20150214208A1
Electricity

Microelectronic assembly having a heat spreader for a plurality of die

#2 | 2015-04-30
US20150115474A1
Electricity

Wirebond recess for stacked die

#3 | 2015-04-30
US20150115463A1
Electricity

Stacked semiconductor devices

#4 | 2014-12-11
US20140363905A1
Physics

Optical wafer and die probe testing

#5 | 2014-12-11
US20140363172A1
Electricity

Die stack with optical TSVs

#6 | 2014-12-11
US20140363153A1
Electricity

Optical die test interface with separate voltages for adjacent electrodes

#7 | 2014-12-11
US20140363124A1
Physics

Optical redundancy

#8 | 2014-12-11
US20140363120A1
Physics

Optical backplane mirror

#9 | 2014-12-11
US20140363119A1
Physics

Integration of a MEMS beam with optical waveguide and deflection in two dimensions

#10 | 2014-12-11
US20140362425A1
Physics

Communication system die stack

#11 | 2014-09-11
US20140252487A1
Electricity

Gate security feature

#12 | 2014-07-17
US20140197541A1
Electricity

Microelectronic assembly having a heat spreader for a plurality of die

#13 | 2014-03-13
US20140071652A1
Electricity

Techniques for reducing inductance in through-die vias of an electronic assembly

#14 | 2014-01-02
US20140001641A1
Electricity

Methods and structures for reducing heat exposure of thermally sensitive semiconductor devices

#15 | 2013-12-05
US20130320480A1
Electricity

Methods and structures for reducing heat exposure of thermally sensitive semiconductor devices

#16 | 2013-07-18
US20130181350A1
Electricity

Semiconductor devices with nonconductive vias

#17 | 2007-03-01
US20070045735A1
Electricity

FinFET structure with contacts

#18 | 2006-10-05
US20060220102A1
Electricity

Process of forming a non-volatile memory cell including a capacitor structure

#19 | 2006-07-06
US20060148196A1
Electricity

Semiconductor fabrication process including recessed source/drain regions in an SOI wafer

#20 | 2006-04-06
US20060073698A1
Electricity

Plasma enhanced nitride layer

#21 | 2006-03-23
US20060063364A1
Electricity

Method of forming a semiconductor device having a metal layer

#22 | 2005-12-15
US20050277276A1
Electricity

Decoupled complementary mask patterning transfer method

#23 | 2005-12-15
US20050277275A1
Electricity

Method for forming a semiconductor device having a silicide layer

#24 | 2005-09-22
US20050205936A1
Electricity

Semiconductor device incorporating a defect controlled strained channel structure and method of making the same

#25 | 2005-05-12
US20050101069A1
Electricity

Confined spacers for double gate transistor semiconductor fabrication process

#26 | 2005-04-07
US20050073028A1
Electricity

Semiconductor device incorporating a defect controlled strained channel structure and method of making the same

InventorID:

340972 ⎘