Inventor profile of:

Shoujun Wang

City:

Kanata

Country:

Canada

Published Applications:

16

Last publication date:

2011-06-30

Top Assignees for applications by Shoujun Wang

The entities that hold a legal rights for patent applications filed by inventor Wang Shoujun:

Recent patent applications by Wang Shoujun

Shoujun Wang from Kanata, CA has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2011-06-30
US20110156806A1
Electricity

Charge pump with reduced current mismatch

#2 | 2011-03-24
US20110068845A1
Electricity

Serializer circuitry for high-speed serial data transmitters on programmable logic device integrated circuits

#3 | 2011-03-08
US12121740
-

Charge pump with reduced current mismatch

#4 | 2010-12-07
US11239703
-

Phase-adjusted pre-emphasis and equalization for data communication

#5 | 2010-11-23
US11259919
-

Duty cycle correction methods and circuits

#6 | 2010-06-22
US11142961
-

Built-in at-speed bit error ratio tester

#7 | 2010-04-06
US11524012
-

Systems and methods for simulating link performance

#8 | 2009-10-06
US10962137
-

Dual-mode LVDS/CML transmitter methods and apparatus

#9 | 2008-11-18
US11169955
-

Dynamic frequency divider with improved leakage tolerance

#10 | 2008-08-21
US20080197906A1
Electricity

Reference clock receiver compliant with LVPECL, LVDS and PCI-Express supporting both AC coupling and DC coupling

#11 | 2008-06-10
US11142880
-

Charge pump with reduced current mismatch

#12 | 2008-04-01
US11484366
-

Reference clock receiver compliant with LVPECL, LVDS and PCI-Express supporting both AC coupling and DC coupling

#13 | 2007-03-29
US20070069831A1
Electricity

Voltage controlled oscillator circuitry and methods

#14 | 2007-02-08
US20070030184A1
Electricity

Serializer circuitry for high-speed serial data transmitters on programmable logic device integrated circuits

#15 | 2007-01-25
US20070019766A1
Electricity

Clock circuitry for programmable logic devices

#16 | 2007-01-04
US20070002993A1
Electricity

Clock data recovery loop with separate proportional path

InventorID:

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