Tad Kwasniewski

Blind adaptive decision feedback equalizer for high-speed serial communications

Zero-delay serial communications circuitry for serial interconnects

Charge pump with reduced current mismatch

Fractional delay-locked loops

Charge pump with reduced current mismatch

Phase-adjusted pre-emphasis and equalization for data communication

Frequency synthesizer circuitry employing delay line

Systems and methods for simulating link performance

Fractional delay-locked loops

APPARATUS FOR TIME-DOMAIN PRE-EMPHASIS AND TIME-DOMAIN EQUALIZATION AND ASSOCIATED METHODS

Digital loop circuit for programmable logic device

APPARATUS FOR POWER CONSUMPTION REDUCTION IN PROGRAMMABLE LOGIC DEVICES AND ASSOCIATED METHODS

Dual-mode LVDS/CML transmitter methods and apparatus

Alignment of clock signal with data signal

Capacitance switch circuitry for digitally controlled oscillators

Apparatus for all-digital serializer-de-serializer and associated methods

Charge pump with reduced current mismatch

Multitap fractional baud period pre-emphasis for data transmission

Differential signal detector methods and apparatus

Voltage controlled oscillator circuitry and methods

Multitap fractional baud period pre-emphasis for data transmission

Clock data recovery loop with separate proportional path

Differential signal detector methods and apparatus

Alignment of recovered clock with data signal

Apparatus and method for wide tuning-range ring oscillators

Apparatus and methods for wide tuning-range ring oscillators

Half-rate linear quardrature phase detector for clock recovery

Input stage threshold adjustment for high speed data communications

Adaptive communication methods and apparatus

Pre-emphasis circuitry and methods