Jochen Preiss

Binary logic unit and method to operate a binary logic unit

Zero indication forwarding for floating point unit power reduction

Reuse of rounder for fixed conversion of log instructions

Shifter with all-one and all-zero detection using a portion of partially shifted vector and shift amount in parallel to generated shifted result

Fast floating point compare with slower backup for corner cases

Distributed residue-checking of a floating point unit

System and method for storing numbers in first and second formats in a register file

Supporting multiple formats in a floating point processor

Normalizer shift prediction for log estimate instructions

3-stack floorplan for floating point unit

Electronic computing circuit for operand width reduction for a modulo adder followed by saturation concurrent message processing

Efficient forcing of corner cases in a floating point rounder

Zero indication forwarding for floating point unit power reduction

Multiplexing output from second execution unit add/saturation processing portion of wider width intermediate result of first primitive execution unit for compound computation

METHOD FOR SIGN-EXTENSION IN A MULTI-PRECISION MULTIPLIER

Semiconductor chip with a plurality of scannable storage elements and a method for scanning storage elements on a semiconductor chip

Binary logic unit and method to operate a binary logic unit

Leading-Zero Counter and Method to Count Leading Zeros

Method and Processor for Performing a Floating-Point Instruction Within a Processor

Floating point unit with fused multiply add and method for calculating a result with a floating point unit