Inventor profile of:

Jitendra Mohan

City:

Santa Clara, California

Country:

United States

Published Applications:

27

Last publication date:

2026-04-07

Top Assignees for applications by Jitendra Mohan

The entities that hold a legal rights for patent applications filed by inventor Mohan Jitendra:

Recent patent applications by Mohan Jitendra

Jitendra Mohan from Santa Clara, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2026-04-07
US18800929
Physics

Virtual metadata storage with decode-alias mitigation

#2 | 2025-05-01
US20250138757A1
Physics

VIRTUAL METADATA STORAGE

#3 | 2025-04-15
US18506387
Physics

Low-latency retimer with seamless clock switchover

#4 | 2024-11-12
US17577759
Electricity

Low-latency signaling-link retimer

#5 | 2023-12-26
US17953458
Physics

Low-latency retimer with seamless clock switchover

#6 | 2022-11-01
US17480051
Physics

Low-latency retimer with seamless clock switchover

#7 | 2022-05-10
US17026454
Physics

Configurable-aggregation retimer with media-dedicated controllers

#8 | 2022-02-22
US16893195
Electricity

Low-latency signaling-link retimer

#9 | 2021-10-19
US16926614
Physics

Low-latency retimer with seamless clock switchover

#10 | 2014-10-28
US11975421
-

System and method for adding a low data rate data channel to a 100Base-T ethernet link

#11 | 2011-09-29
US20110234318A1
Electricity

Low voltage differential signal driver with reduced power consumption

#12 | 2010-09-21
US11342783
-

System and method for providing a strobed comparator with reduced offset and reduced charge kickback

#13 | 2009-12-08
US11036767
-

Driver for vertical-cavity surface-emitting laser and method

#14 | 2009-03-10
US10728065
-

Method of using low bandwidth sensor for measuring high frequency AC modulation amplitude

#15 | 2009-01-13
US11633728
-

Apparatus and method for loss of signal detection in a receiver

#16 | 2009-01-06
US11633727
-

Apparatus and method for high-speed serial communications

#17 | 2008-10-07
US10864099
-

Two-layer electrical substrate for optical devices

#18 | 2008-07-01
US10751674
-

Method for generating non-overlapping N-phases of divide-by-N clocks with precise 1/N duty ratio using a shift register

#19 | 2008-02-19
US10728120
-

Method of sensing VCSEL light output power by monitoring electrical characteristics of the VCSEL

#20 | 2007-05-29
US11036744
-

AC/DC coupling input network with low-power common-mode correction for current-mode-logic drivers

#21 | 2007-04-24
US11161506
-

Differential amplifier with increased common mode loop gain at low frequencies

#22 | 2007-04-24
US11161504
-

Combined analog signal gain controller and equalizer

#23 | 2006-09-12
US10728191
-

Configuration for dockable portable computers using a single ethernet physical layer chip and transformer

#24 | 2006-08-29
US10729389
-

Electrical interconnect with minimal parasitic capacitance

#25 | 2005-11-29
US10734357
-

Inductive-capacitive (LC) based quadrature voltage controlled oscillator (VCO) with deterministic quadrature signal phase relationship

#26 | 2005-09-27
US10751673
-

Fault state detection mechanism for a ring-counter-based frequency divider-by-N that generates non-overlapping N-phases of divide-by-N clocks with 1/N duty ratio

#27 | 2005-08-16
US10061939
-

Band-gap reference circuit with averaged current mirror offsets and method

InventorID:

3445918 ⎘